附带:一.问答题1信号赋值语句在什么情况下作为并行语句?在什么情况下作顺序语句?信号赋值和变量赋值符号分别是什么?两种赋值符号有什么区别?●信号赋值语句在进程外作并行语句,并发执行,与语句所处的位置无关。
信号赋值语句在进程内或子程序内做顺序语句,按顺序执行,与语句所处的位置有关。
●信号赋值符号为“<=”变量赋值用“:=”。
信号赋值符号用于信号赋值动作,不立即生效。
变量,赋值符号用于变量赋值动作,立即生效。
2进程的敏感信号表指的是什么?简述敏感信号表在进程中的作用?●进程的“敏感信号表”也称敏感表,是进程的激活条件,可由一个或多个信号组成,各信号间以“,”号分隔。
当敏感信号表中的任一个信号有事件发生,即发生任意变化,此时,进程被激活,进程中的语句将从上到下逐句执行一遍,当最后一条语句执行完毕之后,进程即进入等待挂起状态,直到下一次敏感表中的信号有事件发生,进程再次被激活,如此循环往复。
3什么是库、程序包、子程序、过程调用和函数调用?●库和程序包用来描述和保存元件、类型说明和子程序等,以便在其它设计中通过其目录可查询、调用。
子程序由过程和函数组成。
在子程序调用过程中,过程能返回多个变量,函数只能返回一个变量。
若子程序调用的是一个过程,就称为过程调用,若子程序调用的是一个函数,则称为函数调用。
过程调用、函数调用都是子程序调用。
二.改错题1.已知sel为STD_LOGIC_VECTOR(1 DOWNTO 0)类型的信号,而a、b、c、d、q均为STD_LOGIC类型的信号,请判断下面给出的CASE语句程序片段:●CASE sel IS●WHEN“00”=>q<=a;●WHEN“01”=>q<=b;●WHEN“10”=>q<=c;●WHEN“11”=>q<=d;●END CASE;●答案:CASE语句缺“WHEN OTHERS”语句。
2.已知data_in1, data_in2为STD_LOGIC_VECTOR(15 DOWNTO 0) 类型的输入端口,data_out为STD_LOGIC_VECTOR(15 DOWNTO 0)类型的输出端口,add_sub为STD_LOGIC类型的输入端口,请判断下面给出的程序片段:●LIBRARY IEEE;●USE IEEE.STD_LOGIC_1164.ALL;●ENTITY add IS● PORT(data_in1, data_in2:IN INTEGER;● data_out:OUT INTEGER);●END add;●ARCHTECTURE add_arch OF add IS●CONSTANT a:INTEGER<=2;●BEGIN●data_out<=( data_in1+ data_in2) * a;●END addsub_arch;答案:常量声明时赋初值的“<=”符号应改用“:=”符号。
3.已知Q为STD_LOGIC类型的输出端口,请判断下面的程序片段:●ARCHITECTURE test_arch OF test IS●BEGIN●SIGNAL B:STD_LOGIC;●Q<= B;END test_arch答案:信号SIGNAL的声明语句应该放在BEGIN语句之前。
4.已知A和Q均为BIT类型的信号,请判断下面的程序片段:●ARCHITECTURE archtest OF test IS●BEGIN●CASE A IS●WHEN ‘0’=>Q<=‘1’;●WHEN ‘1’=>Q<=‘0’;●END CASE;●END archtest;答案:CASE语句应该存在于进程PROCESS内。
三.程序设计LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADDER4B IS --4位二进制并行加法器PORT(CIN:IN STD_LOGIC; --低位进位A: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --4位加数B: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --4位被加数S: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --4位和CONT: OUT STD_LOGIC);END ADDER4B;ARCHITECTURE ART OF ADDER4B ISSIGNAL SINT:STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL AA,BB: STD_LOGIC_VECTOR(4 DOWNTO 0);BEGINAA<='0'& A; --将4位加数矢量扩为5位,为进位提供空间 BB<='0'& B; --将4位被加数矢量扩为5位,为进位提供空间 SINT<=AA+BB+CIN ;S<=SINT(3 DOWNTO 0);CONT<=SINT(4);END ART;2@ 8位二进制加法器的源程序ADDER8B.VHD LIBRARY IEEE;USE IEEE_STD.LOGIC_1164.ALL;USE IEEE_STD.LOGIC_UNSIGNED.ALL:ENTITY ADDER8B IS--由4位二进制并行加法器级联而成的8位二进制加法器PORT(CIN:IN STD_LOGIC;A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);S:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);COUT:OUT STD_LOGIC);END ADDER8B;ARCHICTURE ART OF ADDER8B ISCOMPONENET ADDER4B--对要调用的元件ADDER4B的界面端口进行定义PORT(CIN:IN STD_LOGIC;A:IN STD_LOGIC_VECTOR(3 DOWNTO 0);B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CONT:OUT STD_LOGIC);END COMPONENT ;SIGNAL CARRY_OUT:STD_LOGIC; --4位加法器的进位标志BEGINU1:ADDER4B --例化(安装)一个4位二进制加法器U1PORT MAP(CIN=>CIN,A=>A(3 DOWNTO 0),B=>B(3 DOWNTO0),S=>S(3 DOWNTO 0),COUT=>CARRY_OUT);U2:ADDER4B --例化(安装)一个4位二进制加法器U2PORT MAP(CIN=>CARRY_OUT,A=>A(7 DOWNTO 4),B=>B(7 DOWNTO 4), S=>S (7 DOWNTO 4);CONT=>CONT);END ART;3.@触发器和缓冲器D触发器:Process(clk) beginif(clk’event and clk=‘1’) thenq <= d;end if;end process;缓冲器:Process(clk)beginif(clk=‘1’) thenq <= d;end if; end process;T触发器:Process(clk)beginif(clk’event and clk=‘1’) thenif(t = ‘1’) thenq <= not(q);elseq <= q;end if;end if;end process;4.@16位锁存器的源程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY REG16B IS --16位锁存器PORT (CLK:IN STD_LOGIC;--锁存信号CLR:IN STD_LOGIC;--清零信号D:IN STD_LOGIC_VECTOR (8 DOWNTO 0) --8位数据输入 Q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));--16位数据输出END REG16B;ARCHITECTURE ART OF REG16B ISSIGNAL R16S:STD_LOGIC_VECTOR(15 DOWNTO 0);--16位寄存器设置BEGINPROCESS (CLK,CLR)BEGINIF CLR = '1' THEN R16S<= "00000";--异步复位信号ELSIF CLK'EVENT AND CLK = '1' THEN--时钟到来时,锁存输入值R16S(6 DOWNTO 0)<=R16S(7 DOWNTO 1);--右移低8位R16S(15 DOWNTO 7)<=D;--将输入锁到高能位END IF;END PROCESS;Q<=R16S;END ART;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;--8位右移寄存器ENTITY SREG8B ISPORT (CLK:IN STD_LOGIC; LOAD :IN STD _LOGIC;BIN:IN STD_LOGIC_VECTOR(7DOWNTO 0);QB:OUT STD_LOGIC );END SREG8B;ARCHITECTURE ART OF SREG8B ISSIGNAL REG8B:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS (CLK,LOAD)BEGINIF CLK'EVENT AND CLK= '1' THENIF LOAD = '1' THEN REG8<=DIN;--装载新数据 ELSE REG8(6 DOWNTO0)<=REG8(7 DOWNTO 1);--数据右移END IF;END IF;END PROCESS;QB<= REG8 (0);--输出最低位END ART;6@8位乘法器的源程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; --8位乘法器顶层设计ENTITY MULTI8X8 ISPORT(CLK:IN STD_LOGIC;START:IN STD_LOGIC;--乘法启动信号,高电平复位与加载,低电平运算A:IN STD_LOGIC_VECTOR(7 DOWNTO 0); --8位被乘数B:IN STD_LOGIC_VECTOR(7 DOWNTO 0); --8位乘数ARIEND:OUT STD_LOGIC; --乘法运算结束标志位DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));--16位乘积输出END MULTI8X8;ARCHITECTURE ART OF MULTI8X8 ISCOMPONENT ARICTL --待调用的乘法控制器端口定义PORT(CLK:IN STD_LOGIC;START:IN STD_LOGIC;CLKOUT:OUT STD_LOGIC;RSTALL:OUT STD_LOGIC;ARIEND:OUT STD_LOGIC);END COMPONENT;COMPONENT ANDARITH --待调用的控制与门端口定义PORT(ABIN:IN STD_LOGIC;DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);DOUT:OUT_STD_LOGIC_VECTOR( 7 DOWNTO 0) );END COMPONENT;COMPONENT ADDER8B --待调用的8位加法器端口定义COMPONENT SREG8B --待调用的8位右移寄存器端口定义...COMPONENT REG16B --待调用的16右移寄存器端口定义...SIGNAL GNDINT:STD_LOGIC;SIGNAL INTCLK:STD_LOGIC;SIGNAL RSTALL:STD_LOGIC;SIGNAL QB:STD_LOGIC;SIGNAL ANDSD:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL DTBIN:STD_LOGIC_VECTOR(8 DOWNTO 0);SIGNAL DTBOUT:STD_LOGIC_VECTOR(15 DOWNTO 0);BEGINDOUT<=DTBOUT;GNDINT<= '0';U1:ARICTL PORT MAP(CLK=>CLK, START=>START,CLKOUT=>INTCLK, RSTALL=>RSTALL, ARIEND=>ARIEND);U2:SREG8B PORT MAP(CLK=>INTCLK, LOAD=>RSTALL.DIN=>B, QB=>QB);U3:ANDARITH PORT MAP(ABIN=>QB,DIN=>A,DOUT=>ANDSD);U4:ADDER8B PORTMAP(CIN=>GNDINT,A=>DTBOUT(15 DOWNTO 8),B=>ANDSD, S=>DTBIN(7 DOWNTO 0),COUT =>DTBIN(8));U5:REG16B PORT MAP(CLK =>INTCLK,CLR=>RSTALL,D=>DTBIN, Q=>DTBOUT);END ART;7@有时钟使能的十进制计数器的源程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;--有时钟使能的十进制计数器ENTITY CNT10 ISPORT (CLK:IN STD_LOGIC;--计数时钟信号CLR:IN STD_LOGIC;--清零信号END:IN STD_LOGIC;--计数使能信号CQ:OUT INTEGER RANGE 0 TO 15; --4位计数结果输出CARRY_OUT:OUT STD_LOGIC); --计数进位END CNT10;ARCHITECTURE ART OF CNT10 ISSIGNAL CQI :INTEGER RANGE 0 TO 15;BEGINPROCESS(CLK,CLR,ENA)BEGINIF CLR= '1' THEN CQI<= 0;--计数器异步清零ELSIF CLK'EVENT AND CLK= '1' THENIF ENA= '1' THENIF CQI<9 THEN CQI<=CQI+1;ELSE CQI<=0;END IF;--等于9,则计数器清零END IF;END IF;END PROCESS;PROCESS (CQI)BEGINIF CQI=9 THEN CARRY_OUT<= '1';--进位输出ELSE CARRY_OUT<= '0';END IF;END PROCESS;CQ<=CQI;END ART;8@) 六进制计数器的源程序CNT6.VHD(十进制计数器的源程序CNT10.VHD与此类似)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT6 ISPORT (CLK:IN STD_LOGIC;CLR:IN STD_LOGIC;ENA: IN STD_LOGIC;CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);CARRY_OUT: OUT STD_LOGIC );END CNT6;ARCHITECTURE ART OF CNT6 ISSIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,CLR,ENA)BEGINIF CLR='1' THEN CQI<="0000";ELSIF CLK'EVENT AND CLK='1' THENIF ENA='1' THENIF CQI=“0101” THEN CQI<=“0000”;ELSE CQI<=CQI+'1';END IF;END IF;END IF;END PROCESS;PROCESS(CQI)BEGINIF CQI=“0000” THEN CARRY_O UT<='1';ELSE CARRY_OUT<='0';END IF;END PROCESS;CQ<=CQI;END ART;9@十进制计数器LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY count10 ISPORT(clk: IN STD_LOGIC;seg: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));END count10;ARCHITECTURE a1 OF count10 ISsignal sec: STD_LOGIC;signal q : STD_LOGIC_VECTOR(21 DOWNTO 0);signal num: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINprocess(clk) ----get 1 hz clock pulsebeginif clk'event and clk='1' then q<=q+1; end if;sec<=q(21); --get 1 hz clock pulseend process;timing: process(sec) beginif sec'event and sec='1' thenif num<9 then num<=num+1; else num<="0000"; end if; end if;end process;B1: block --bcd-7segsBegin --gfedcbaseg<= "0111111" when num=0 else"0000110" when num=1 else"1011011" when num=2 else"1001111" when num=3 else"1100110" when num=4 else"1101101" when num=5 else"1111101" when num=6 else"0000111" when num=7 else"1111111" when num=8 else"1101111" when num=9 else"0000000";end block;END a1;10@4MHz到1Hz的分频器LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY count ISPORT( clk: in STD_LOGIC;q: out STD_LOGIC;END count;ARCHITECTURE a OF count ISsignal tmp: STD_LOGIC_vector(21 downto 0);Beginprocess(clk) beginif clk'event and clk='1' then tmp<=tmp+1;end if; end process;q<=tmp(21);END a;11@与门ENTITY shili2 isport (input1 : in std_logic; inptu2 : in std_logic; output1 : out std_logic );end entity;architecture one of shili2 is beginoutput1<=input1 and input2; end entity;12@.四输入与门电路library ieee;use ieee.std_logic_1164.all;entity and4 isport(a,b,c,d:in std_logic; y:out std_logic; end and4;architecture and4_1 of and4 is beginy<= a and b and c and d;end nand4_1; 法二(与非门):library ieee;use ieee.std_logic_1164.all entity nand4 isport(a.b,c,d:in std_logic;y:out std_logic); end nand4;architecture nand4_2 of nand4 si beginp1:process(a,b,c,d)variabletmp:std_logic_vector(3 downto 0); begintmp:=a&b&c&d;case tmp iswhen"0000"=>y<='1';when"0001"=>y<='1';when"0010"=>y<='1';when"0011"=>y<='1';when"0100"=>y<='1';when"0101"=>y<='1';when"0110"=>y<='1';when"0111"=>y<='1';when"1000"=>y<='1';when"1001"=>y<='1';when"1010"=>y<='1';when"1011"=>y<='1';when"1100"=>y<='1';when"1101"=>y<='1';when"1110"=>y<='1';when"1111"=>y<='1';when others=>y<='x';end case;end process;end nand4_2;13@四位全加器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity add isport(a,b:in std_logic_vector(3 downto 0); cin:in std_logic;s:out std_logic_vector(3 downto 0); cout:out std_logic);end add;architecture beh of add isbeginprocess(a,b,cin)ariable x:std_logic_vector(3 downto 0); variable m,n,l:integer;beginm:=conv_integer(a);n:=conv_integer(b);l:=m+n+conv_integer(cin);x:=conv_std_logic_vector(l,4);s<=x(3 downto 0);cout<=x(3);end process;end beh;14@N位移位寄存器:page7015@8位通用寄存器:page13716@串入串出移位寄存器:page13817@10位计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT ( CLK ,clr : IN STD_LOGIC ;CQ : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ));END ENTITY CNT10;ARCHITECTURE ONE OF CNT10 ISBEGINPROCESS ( CLK , clr )VARIABLE LCQ : STD_LOGIC_VECTOR ( 3 DOWNTO 0 );BEGINIF RST = ‘1’ THEN LCQ := “0000”;ELSIF CLK’EVENT AND CLK = ‘1’ THENIF LCQ < 9 THEN LCQ := LCQ + 1;ELSE LCQ := “0000” ;END IF; END IF;CQ <= LCQ ;END PROCESS;END ARCHITECTURE ONE;18@八位串行二进制全加器use ieee.std_logic_1164.all;entity product_adder_subtracter isport(a,b:in std_logic_vector(7 downto 0);s:out std_logic_vector(8 downto 0));end;architecture behavioral of product_adder_subtracter isbeginbehavior:process(a,b) isvariable carry_in:std_logic;variable carry_out:std_logic;variable op2:std_logic_vector(b'range);beginop2:=b;end if;for index in 0 to 7 loopcarry_in:=carry_out;s(index)<=a(index) xor op2(index)xor carry_in ;carry_out:=(a(index)and op2(index))or(carry_in and (a(index) xor op2(index))); end loop;s(8)<=a(7) xor op2(7) xor carry_out;end process;end;EDA知识要点:1、目前流行的HDL语言有那些?;2、什么是ASIC。