南昌大学实验报告学生姓名：学号：专业班级：实验类型：□验证□综合 设计□创新实验日期：实验成绩：实验三序列信号发生检测器一、实验目的1、学会运用VHDL语言设计方法构建具有一定逻辑功能的模块，并能运用图形设计方法完成顶层原理图的设计。

2、掌握脉冲序列检测器的主要功能二、实验要求1、设计一个序列信号发生器，用以产生输入序列“1101010011010101”由左开始。

2、设计一个序列检测器，用以检测输入序列，检测序列为100113、运用QuartusⅡ软件中的仿真功能对所设计的序列检测器的各个模块及顶层电路的功能进行仿真分析。

三、设计过程1，序列信号检测器设计原理：序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号，当序列检测器连续收到一组串行二进制码后，如果这组码与检测器中预先设置的相同，则输出 1，否则输出 0。

由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到在连续的检测中所收到的每一位码与预置数的对应码相同。

设计中一般采用状态机来实现。

2，模块设计：根据层次化设计理论以及序列信号检测器的基本原理，本次设计的序列检测器采用自顶向下的思路可分为时钟输入模块、序列发生模块、序列检测模块、数码管动态扫描显示模块及LED状态转换显示模块，系统框图如下序列信号检测器系统框图3、使用文本设计底层文件，并生成相应元器件，再使用原理图设计顶层文件四、实验步骤1、顶层文件的设计顶层原理图设计可以依据系统框图进行，时钟输入模块（clkdiv）、序列发生模块（fsq）、序列检测模块（jcq）、数码管动态扫描显示模块及LED状态转换显示模块（scan_led）、序列信号译码模块（czb）2，各模块设计文件①时钟clkdiv:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DIV ISPORT(CLK : IN STD_LOGIC;CLK_DIV : OUT STD_LOGIC);END DIV;ARCHITECTURE RT1 OF DIV ISSIGNAL DA TA:INTEGER RANGE 0 TO 500;SIGNAL CLK_TEMP:STD_LOGIC;BEGINPROCESS(CLK)BEGINIF RISING_EDGE(CLK) THENIF(DA TA=500) THENDA TA<=0;CLK_TEMP<=NOT CLK_TEMP;ELSEDA TA<=DATA+1;END IF;END IF;CLK_DIV<=CLK_TEMP;END PROCESS;END RT1;②序列发生器FSQ：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY FSQ ISPORT(CLK,CLEA:IN STD_LOGIC;Z :OUT STD_LOGIC);END FSQ ;ARCHITECTURE RTL OF FSQ ISTYPE STA TE_TYPE IS(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15);SIGNAL CURRENT_STATE,NEXT_STA TE:STATE_TYPE;BEGINPROCESS(CLK,CLEA)BEGINIF(CLEA='1')THEN CURRENT_STATE<=S0;ELSEIF(CLK'EVENT AND CLK='1')THENCURRENT_STATE<=NEXT_STATE;END IF;END IF;END PROCESS;STATE_TRANS:PROCESS(CURRENT_STATE) BEGINCASE CURRENT_STATE ISWHEN S0=> NEXT_STATE<=S1; Z<='1';WHEN S1=> NEXT_STATE<=S2; Z<='1';WHEN S2=> NEXT_STATE<=S3; Z<='0';WHEN S3=> NEXT_STATE<=S4; Z<='1';WHEN S4=> NEXT_STATE<=S5; Z<='0';WHEN S5=> NEXT_STATE<=S6; Z<='1';WHEN S6=> NEXT_STATE<=S7; Z<='0';WHEN S7=> NEXT_STATE<=S8; Z<='0';WHEN S8=> NEXT_STATE<=S9; Z<='1';WHEN S9=> NEXT_STATE<=S10; Z<='1';WHEN S10=> NEXT_STA TE<=S11; Z<='0';WHEN S11=> NEXT_STA TE<=S12; Z<='1';WHEN S12=> NEXT_STA TE<=S13; Z<='0';WHEN S13=> NEXT_STA TE<=S14; Z<='1';WHEN S14=> NEXT_STA TE<=S15; Z<='0';WHEN S15=> NEXT_STA TE<=S0; Z<='1';END CASE;END PROCESS;END RTL;③序列检测器JCQLIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JCQ ISPORT(SIN, CLK, CLR : IN STD_LOGIC;PUT : OUT std_logic_vector(0 downto 0));END JCQ;ARCHITECTURE one OF JCQ ISTYPE STA is (S5,S4,S3,S2,S1,S0);SIGNAL Qe : STA ;SIGNAL D : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIND <= "11010" ;PROCESS( CLK, CLR )BEGINIF CLR = '1' THEN Qe <= S0 ;ELSIF CLK'EVENT AND CLK='1' THENCASE Qe ISWHEN S0=> IF SIN = D(4) THEN Qe <= S1 ; ELSE Qe <= S0 ; END IF ; WHEN S1=> IF SIN = D(3) THEN Qe <= S2 ; ELSE Qe <= S0 ; END IF ; WHEN S2=> IF SIN = D(2) THEN Qe <= S3 ; ELSE Qe <= S2 ; END IF ; WHEN S3=> IF SIN = D(1) THEN Qe <= S4 ; ELSE Qe <= S0 ; END IF ; WHEN S4=> IF SIN = D(0) THEN Qe <= S5 ; ELSE Qe <= S2 ; END IF ; WHEN OTHERS => Qe <= S0 ;END CASE ;END IF ;END PROCESS ;PROCESS( Qe )BEGINIF Qe = S5 THEN PUT <= "1";ELSE PUT <= "0";END IF ;END PROCESS ;END one ;④序列译码CZBLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY czb ISPORT(clk,din:in std_logic;dout:out std_logic_vector(4 downto 0));end entity czb;architecture behave of czb isbeginprocess(clk)variable i:integer range 0 to 5;variable t:std_logic_vector(4 downto 0);beginif clk='1' thent(4 downto 0):=t(3 downto 0)&din;i:=i+1;dout<=t;if i=5 theni:=0;end if;end if;end process;end architecture behave;⑤数码管及LED显示SCAN_LED：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY scan_led ISPORT(clk : IN STD_LOGIC;data: IN STD_LOGIC_VECTOR(4 DOWNTO 0);data0: IN STD_LOGIC_VECTOR(0 DOWNTO 0);scan : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);choose: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END ENTITY;ARCHITECTURE one OF scan_led ISSIGNAL cout8:STD_LOGIC_VECTOR(2 DOWNTO 0);SIGNAL A :STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINP1:PROCESS(cout8)BEGINCASE cout8 ISWHEN "000" => choose <= "000"; A <= "000"&data(4);WHEN "001" => choose <= "001"; A <= "000"&data(3);WHEN "010" => choose <= "010"; A <= "000"&data(2);WHEN "011" => choose <= "011"; A <= "000"&data(1);WHEN "100" => choose <= "100"; A <= "000"&data(0);WHEN "101" => choose <= "101"; A <= "1000";WHEN "110" => choose <= "110"; A <= "1000";WHEN "111" => choose <= "111"; A <= "000"&data0;WHEN OTHERS => NULL;END CASE;END PROCESS P1;P2:PROCESS(clk)BEGINIF clk'EVENT AND clk ='1' THEN cout8 <= cout8+1;END IF;END PROCESS P2;P3:PROCESS(A)BEGINCASE A ISWHEN "0000"=> scan <="0111111";WHEN "0001"=> scan <="0000110";WHEN "1000"=> scan <="1000000";WHEN OTHERS=> NULL;END CASE;END PROCESS P3;END;3、编译1）输入完程序之后逐个编译2）逐个编译无错之后进行全程编译4、将以上模块生成元器件，连接成实验电路图5、系统仿真1）建立新的波形激励文件2）在波形编辑器窗口添加节点3）通过Edit->End Time 来设定仿真结束时间4）在CLOCK窗口中设置clk的时钟周期为60s5）点击save保存6) 通过Tools下的Simulator Tools项进行仿真，然后观察输出波形。