Laboratory Exercise 1Switches, Lights, and Multiplexers ED实验参与答案Part1library ieee;use ieee.std_logic_1164.all;entity part1 isport(SW:in std_logic_vector(17 downto 0);LEDR:out std_logic_vector(17 downto 0));end part1;architecture Behavior of part1 isbeginLEDR <= SW;end Behavior;part2library ieee;use ieee.std_logic_1164.all;--a 2 to 1 multiplexer entityentity mux21 isport(in_x, in_y, in_s:in std_logic;out_m:out std_logic);end mux21;--a 2 to 1 multiplexer architecturearchitecture structural of mux21 issignal u, v:std_logic;beginu <= in_x and (not in_s);v <= in_y and in_s ;out_m <= u or v ;end structural;--a eight-bit wide 2 to 1 multiplexerlibrary ieee;use ieee.std_logic_1164.all;--eight-bit wide 2 to 1 multiplexer entityentity mux21_8bit isport(SW: in std_logic_vector (17 downto 0);--SW: in std_logic_vector (15 downto 8);--SW: in std_logic_vector (17 downto 17);LEDR: out std_logic_vector (7 downto 0));end mux21_8bit;--eight-bit wide 2 to 1 multiplexera rchitecturearchitecture Structural of mux21_8bit iscomponent mux21port(in_x, in_y, in_s:in std_logic;out_m:out std_logic);end component;beginU1:mux21port map (in_x=>SW(0), in_y=>SW(8), in_s=>SW(17), out_m=>LEDR(0));U2:mux21port map (in_x=>SW(1), in_y=>SW(9), in_s=>SW(17), out_m=>LEDR(1));U3:mux21port map (in_x=>SW(2), in_y=>SW(10), in_s=>SW(17), out_m=>LEDR(2));U4:mux21port map (in_x=>SW(3), in_y=>SW(11), in_s=>SW(17), out_m=>LEDR(3));U5:mux21port map (in_x=>SW(4), in_y=>SW(12), in_s=>SW(17), out_m=>LEDR(4));U6:mux21port map (in_x=>SW(5), in_y=>SW(13), in_s=>SW(17), out_m=>LEDR(5));U7:mux21port map (in_x=>SW(6), in_y=>SW(14), in_s=>SW(17), out_m=>LEDR(6));U8:mux21port map (in_x=>SW(7), in_y=>SW(15), in_s=>SW(17), out_m=>LEDR(7));end Structural;part3library ieee;use ieee.std_logic_1164.all;--a 2 to 1 multiplexer entityentity mux21 isport(in_x, in_y, in_s:in std_logic;out_m:out std_logic);end mux21;--a 2 to 1 multiplexer architecturearchitecture structural of mux21 issignal signal_u, signal_v:std_logic;beginsignal_u <= in_x and (not in_s);signal_v <= in_y and in_s ;out_m <= signal_u or signal_v ;end structural;library ieee;use ieee.std_logic_1164.all;--a 5 to 1 multiplexer entityentity mux51 isport(in5_u, in5_v, in5_w, in5_x, in5_y, in5_s1, in5_s2, in5_s0:in std_logic;out5_m:out std_logic);end mux51;--a 5 to 1 multiplexer architecturearchitecture Structural of mux51 iscomponent mux21port (in_x, in_y, in_s:in std_logic;out_m:out std_logic);end component;signal signal_a, signal_b, signal_c:std_logic;beginU1:mux21port map (in_x=>in5_u, in_y=>in5_v, in_s=>in5_s0, out_m=>signal_a);U2:mux21port map (in_x=>in5_w, in_y=>in5_x, in_s=>in5_s0, out_m=>signal_b);U3:mux21port map (in_x=>signal_a, in_y=>signal_b, in_s=>in5_s1, out_m=>signal_c);U4:mux21port map (in_x=>signal_c, in_y=>in5_y, in_s=>in5_s2, out_m=>out5_m);end Structural;library ieee;use ieee.std_logic_1164.all;--a 3bit 5 to 1 multiplexer entityentity mux51_3bit isport(SW: in std_logic_vector (17 downto 0);LEDR: out std_logic_vector (17 downto 0);LEDG: out std_logic_vector (2 downto 0));end mux51_3bit;--a 3bit 5 to 1 multiplexer architecturearchitecture structural of mux51_3bit iscomponent mux51port(in5_u, in5_v, in5_w, in5_x, in5_y, in5_s1, in5_s2, in5_s0:in std_logic;out5_m:out std_logic);end component;beginLEDR <= sw;U1:mux51 port map (in5_u=>SW(0), in5_v=>SW(3), in5_w=>SW(6), in5_x=>SW(9), in5_y=>SW(12),in5_s0=>SW(15), in5_s1=>SW(16), in5_s2=>SW(17), out5_m=>LEDG(0));U2:mux51 port map (in5_u=>SW(1), in5_v=>SW(4), in5_w=>SW(7), in5_x=>SW(10), in5_y=>SW(13),in5_s0=>SW(15), in5_s1=>SW(16), in5_s2=>SW(17), out5_m=>LEDG(1));U3:mux51 port map (in5_u=>SW(2), in5_v=>SW(5), in5_w=>SW(8), in5_x=>SW(11), in5_y=>SW(14),in5_s0=>SW(15), in5_s1=>SW(16), in5_s2=>SW(17), out5_m=>LEDG(2));end structural;part4library ieee;use ieee.std_logic_1164.all;--a 7-segment decoder entityentity decoder isport(decoder_in_3:in std_logic_vector(2 downto 0);HEX0:out std_logic_vector(0 to 6));end decoder;-- a 7-segment decorder architecturearchitecture behavioral of decoder isbeginprocess(decoder_in_3)begincase decoder_in_3 iswhen "000"=> HEX0<= "0001001";when "001"=> HEX0 <= "0000110";when "010"=> HEX0 <= "1000110";when "011"=> HEX0 <= "1000000";when others => Hex0 <= "1111111";end case;end process;end behavioral;part5library ieee;use ieee.std_logic_1164.all;entity part5 isport(SW: in std_logic_vector(17 downto 0);HEX0,HEX1,HEX2,HEX3,HEX4: out std_logic_vector(6 downto 0));end part5;architecture Behavior of part5 iscomponent mux51_seg7port(Mux51_seg7_in: in std_logic_vector(17 downto 0);Seg: out std_logic_vector(6 downto 0));end component;beginU0:mux51_seg7port map(Mux51_seg7_in=>SW,Seg=>HEX0);U1:mux51_seg7port map(Mux51_seg7_in(17 downto 15)=>SW(17 downto 15), Mux51_seg7_in(14 downto 12)=>SW(11 downto 9),Mux51_seg7_in(11 downto 9)=>SW(8 downto 6), Mux51_seg7_in(8 downto 6)=>SW(5 downto 3),Mux51_seg7_in(5 downto 3)=>SW(2 downto 0), Mux51_seg7_in(2 downto 0)=>SW(14 downto 12),Seg=>HEX1);U2:mux51_seg7port map(Mux51_seg7_in(17 downto 15)=>SW(17 downto 15), Mux51_seg7_in(14 downto 12)=>SW(8 downto 6),Mux51_seg7_in(11 downto 9)=>SW(5 downto 3), Mux51_seg7_in(8 downto 6)=>SW(2 downto 0),Mux51_seg7_in(5 downto 3)=>SW(14 downto 12), Mux51_seg7_in(2 downto 0)=>SW(11 downto 9),Seg=>HEX2);U3:mux51_seg7port map(Mux51_seg7_in(17 downto 15)=>SW(17 downto 15), Mux51_seg7_in(14 downto 12)=>SW(5 downto 3),Mux51_seg7_in(11 downto 9)=>SW(2 downto 0), Mux51_seg7_in(8 downto 6)=>SW(14 downto 12),Mux51_seg7_in(5 downto 3)=>SW(11 downto 9), Mux51_seg7_in(2 downto 0)=>SW(8 downto 6),Seg=>HEX3);U4:mux51_seg7port map(Mux51_seg7_in(17 downto 15)=>SW(17 downto 15), Mux51_seg7_in(14 downto 12)=>SW(2 downto 0),Mux51_seg7_in(11 downto 9)=>SW(14 downto 12), Mux51_seg7_in(8 downto 6)=>SW(11 downto 9),Mux51_seg7_in(5 downto 3)=>SW(8 downto 6), Mux51_seg7_in(2 downto 0)=>SW(5 downto 3),Seg=>HEX4);end Behavior;----------------------------------------------------------------------------------------------------------A circuit that can select and display one of five characters-----------------------------------------------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;entity mux51_seg7 isport(Mux51_seg7_in: in std_logic_vector(17 downto 0);Seg: out std_logic_vector(6 downto 0));end mux51_seg7;architecture Behavior of mux51_seg7 iscomponent mux51_3bitport(S, U, V, W, X, Y: in std_logic_vector(2 downto 0);M: out std_logic_vector(2 downto 0));end component;component char_7segport(C: in std_logic_vector(2 downto 0);Display: out std_logic_vector(6 downto 0));end component;signal M : std_logic_vector(2 downto 0);beginM0: mux51_3bit port map(Mux51_seg7_in(17 downto 15), Mux51_seg7_in(14 downto 12),Mux51_seg7_in(11 downto 9),Mux51_seg7_in(8 downto 6),Mux51_seg7_in(5 downto 3),Mux51_seg7_in(2 downto 0),M);H0: char_7seg port map(M, Seg);end Behavior;-----------------------------------------------------------------------------------------------------------------------------a 3bit mux51----------------------------------------------------------------------------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;--a 2 to 1 multiplexer entityentity mux21 isport(in_x, in_y, in_s:in std_logic;out_m:out std_logic);end mux21;--a 2 to 1 multiplexer architecturearchitecture structural of mux21 issignal signal_u, signal_v:std_logic;beginsignal_u <= in_x and (not in_s);signal_v <= in_y and in_s ;out_m <= signal_u or signal_v ;end structural;library ieee;use ieee.std_logic_1164.all;--a 5 to 1 multiplexer entityentity mux51 isport(in5_u, in5_v, in5_w, in5_x, in5_y, in5_s1, in5_s2, in5_s0:in std_logic;out5_m:out std_logic);end mux51;--a 5 to 1 multiplexer architecturearchitecture Structural of mux51 iscomponent mux21port (in_x, in_y, in_s:in std_logic;out_m:out std_logic);end component;signal signal_a, signal_b, signal_c:std_logic;beginU1:mux21port map (in_x=>in5_u, in_y=>in5_v, in_s=>in5_s0, out_m=>signal_a);U2:mux21port map (in_x=>in5_w, in_y=>in5_x, in_s=>in5_s0, out_m=>signal_b);U3:mux21port map (in_x=>signal_a, in_y=>signal_b, in_s=>in5_s1, out_m=>signal_c);U4:mux21port map (in_x=>signal_c, in_y=>in5_y, in_s=>in5_s2, out_m=>out5_m);end Structural;-----------------------------------------------------------------------------------------------------------------------------a 3bit 5 to 1 multiplexer---------------------------------------------------------------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;--a 3bit 5 to 1 multiplexer entityentity mux51_3bit isport(S, U, V, W, X, Y: in std_logic_vector (2 downto 0);M: out std_logic_vector (2 downto 0));end mux51_3bit;--a 3bit 5 to 1 multiplexer architecturearchitecture structural of mux51_3bit iscomponent mux51port(in5_u, in5_v, in5_w, in5_x, in5_y, in5_s1, in5_s2, in5_s0:in std_logic;out5_m:out std_logic);end component;beginU1:mux51 port map (in5_u=>U(0), in5_v=>V(0), in5_w=>W(0), in5_x=>X(0), in5_y=>Y(0),in5_s0=>S(0), in5_s1=>S(1), in5_s2=>S(2), out5_m=>M(0));U2:mux51 port map (in5_u=>U(1), in5_v=>V(1), in5_w=>W(1), in5_x=>X(1), in5_y=>Y(1),in5_s0=>S(0), in5_s1=>S(1), in5_s2=>S(2), out5_m=>M(1));U3:mux51 port map (in5_u=>U(2), in5_v=>V(2), in5_w=>W(2), in5_x=>X(2), in5_y=>Y(2),in5_s0=>S(0), in5_s1=>S(1), in5_s2=>S(2), out5_m=>M(2));end structural;-----------------------------------------------------------------------------------------------------------------------------a 7-segment decoder---------------------------------------------------------------------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;--a 7-segment decoder entityentity char_7seg isport(C:in std_logic_vector(2 downto 0);Display:out std_logic_vector(6 downto 0));end char_7seg;-- a 7-segment decorder architecturearchitecture behavioral of char_7seg isbeginprocess(C)begincase C iswhen "000"=> Display <= "0001001";when "001"=> Display <= "0000110";when "010"=> Display <= "1000111";when "011"=> Display <= "1000000";when others => Display <= "1111111";end case;end process;end behavioral;part6--------------------------------------------------------------------------------------------------------------Rotating the word HELLO on eight displays.----------------------------------SW(17~15): select--SW(14~12): H--SW(11~9):E--SW(8~6):L--SW(5~3):O--SW(2~0):none---------------------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;entity part6 isport(SW: in std_logic_vector(17 downto 0);HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7: out std_logic_vector(6 downto 0)); end part6;architecture Behavior of part6 iscomponent mux81_seg7port(S, D0, D1, D2, D3, D4, D5, D6, D7: in std_logic_vector(2 downto 0);Seg: out std_logic_vector(6 downto 0));end component;beginU0:mux81_seg7port map(S=>SW(17 downto 15),D0=>SW(2 downto 0),D1=>SW(2 downto 0),D2=>SW(2 downto 0),D3=>SW(14 downto 12),D4=>SW(11 downto 9),D5=>SW(8 downto 6),D6=>SW(8 downto 6),D7=>SW(5 downto 3),Seg=>HEX0);U1:mux81_seg7port map(S=>SW(17 downto 15),D0=>SW(2 downto 0),D1=>SW(2 downto 0),D2=>SW(14 downto 12),D3=>SW(11 downto 9),D4=>SW(8 downto 6),D5=>SW(8 downto 6),D6=>SW(5 downto 3),D7=>SW(2 downto 0),Seg=>HEX1);U2:mux81_seg7port map(S=>SW(17 downto 15),D0=>SW(2 downto 0),D1=>SW(14 downto 12),D2=>SW(11 downto 9),D3=>SW(8 downto 6),D4=>SW(8 downto 6),D5=>SW(5 downto 3),D6=>SW(2 downto 0),D7=>SW(2 downto 0),Seg=>HEX2);U3:mux81_seg7port map(S=>SW(17 downto 15),D0=>SW(14 downto 12),D1=>SW(11downto 9),D2=>SW(8 downto 6),D3=>SW(8 downto 6),D4=>SW(5 downto 3),D5=>SW(2 downto 0),D6=>SW(2 downto 0),D7=>SW(2 downto 0),Seg=>HEX3);U4:mux81_seg7port map(S=>SW(17 downto 15),D0=>SW(11 downto 9),D1=>SW(8 downto 6),D2=>SW(8 downto 6),D3=>SW(5 downto 3),D4=>SW(2 downto 0),D5=>SW(2 downto 0),D6=>SW(2 downto 0),D7=>SW(14 downto 12),Seg=>HEX4);U5:mux81_seg7port map(S=>SW(17 downto 15),D0=>SW(8 downto 6),D1=>SW(8 downto 6),D2=>SW(5 downto 3),D3=>SW(2 downto 0),D4=>SW(2 downto 0),D5=>SW(2 downto 0),D6=>SW(14 downto 12),D7=>SW(11 downto 9),Seg=>HEX5);U6:mux81_seg7port map(S=>SW(17 downto 15),D0=>SW(8 downto 6),D1=>SW(5 downto 3),D2=>SW(2 downto 0),D3=>SW(2 downto 0),D4=>SW(2 downto 0),D5=>SW(14 downto 12),D6=>SW(11 downto 9),D7=>SW(8 downto 6),Seg=>HEX6);U7:mux81_seg7port map(S=>SW(17 downto 15),D0=>SW(5 downto 3),D1=>SW(2 downto 0),D2=>SW(2 downto 0),D3=>SW(2 downto 0),D4=>SW(14 downto 12),D5=>SW(11 downto 9),D6=>SW(8 downto 6),D7=>SW(8 downto 6),Seg=>HEX7);end Behavior;----------------------------------------------------------------------------------------------------------A circuit that can select and display one of eight characters----------------------------------------------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;--eht mux81_seg7 entityentity mux81_seg7 isport(S, D0, D1, D2, D3, D4, D5, D6, D7: in std_logic_vector(2 downto 0);Seg: out std_logic_vector(6 downto 0));end mux81_seg7;--the mux81_seg7 architecturearchitecture Behavior of mux81_seg7 iscomponent mux81_3bitport(S, D0, D1, D2, D3, D4, D5, D6, D7: in std_logic_vector(2 downto 0);M: out std_logic_vector(2 downto 0));end component;component char_7segport(C: in std_logic_vector(2 downto 0);Display: out std_logic_vector(6 downto 0));end component;signal M1 : std_logic_vector(2 downto 0);beginM0: mux81_3bit port map(S, D0, D1, D2, D3, D4, D5, D6, D7,M1);H0: char_7seg port map(M1, Seg);end Behavior;-----------------------------------------------------------------------------------------------------------------------------a 3bit mux81----------------------------------------------------------------------------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;--a 3bit multiplexer 8 to 1 entityentity mux81_3bit isport(S, D0, D1, D2, D3, D4, D5, D6, D7: in std_logic_vector(2 downto 0);M: out std_logic_vector(2 downto 0)); end mux81_3bit;--a 3bit multiplexer 8 to 1 architecturearchitecture behavioral of mux81_3bit isbeginwith S selectM <= D0when "000",D1 when "001",D2 when "010",D3 when "011",D4 when "100",D5 when "101",D6 when "110",D7 when "111","ZZZ"when others;end behavioral;-----------------------------------------------------------------------------------------------------------------------------a 7-segment decoder---------------------------------------------------------------------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;--a 7-segment decoder entityentity char_7seg isport(C:in std_logic_vector(2 downto 0);Display:out std_logic_vector(6 downto 0));end char_7seg;-- a 7-segment decorder architecturearchitecture behavioral of char_7seg isbeginprocess(C)begincase C iswhen "000"=> Display <= "0001001";when "001"=> Display <= "0000110";when "010"=> Display <= "1000111";when "011"=> Display <= "1000000";when others => Display <= "1111111";end case;end process;end behavioral;。