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数字机顶盒原理图GOSPELL


RN1 2K2RP C49 C44 C45 104 104 R88 R90 8 7 6 5 C50 RN2 3K3RP AGC SDA SCL 104 Q NC NC 104 I
B
B
VINPQ VINNQ VINNI VINPI
1 2 3 4
2
1 2 3 4
R91 R92
33R 33R
TDA TCL BC30 C46 33PF 33PF C47 33PF
C
1K
2
CN502 PJ-320D 2 3 4 3CVBS/2Y 2 3 4 1 6 5 1 6 5
R65
B
75R
B
A
A
5
4
3
2
1
5
4
3
2
1
+3.3V_FLASH_SDRAM +3.3V_FLASH_SDRAM S_CSJ S_MISO S_MOSI S_SLK
D
S_CSJ S_MISO S_MOSI S_SLK
2 2
GND SLK_S S_MOSI
DQML DQMH SDCLK BA0 BA1 SWEN CASN RASN
2 2 2 2 2 2 2 2
GND
EN25F16-100HIP 16Mbit
S_SLK
R26
33R
SLK_S C110 10pF
EMI cap.
C
C
GND
2 2
SD[0..15] SA[0..11] SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 DQML DQMH SWEN CASN RASN R112 4K7 R107 33R 23 24 25 26 29 30 31 32 33 34 22 35 15 39 16 17 18 19 37 38 20 21 6 12 46 52 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 LDQM UDQM WE CAS RAS CS CKE CLK BA0 BA1 VSSq VSSq VSSq VSSq
R105 4K7
BC33 102 LNB_POWER
BC25 104 +3.3V_I/O +3.3V_TUNER
102
CPU_CLOCK 1 BC67 10uF/25V_1206 BC28 104 BC29 104
1
BC66 10uF/25V_1206
+
2
EC24 47uF/50V
BC35 104
8 7 6 5
1
BC39 104
1
7
U13 8 1 2 3 4 BC63 101 S S S G D D D D 8 7 6 5
2
L14 FBEAD 2 1
+3.3V_TUNER 120mA~180mA
+3.3V_TUNER
6
4
3K
R140 AT1380AP(TSSOP) 2K BC62 R137 104
ME4436(SOP)_NC
R144 104 1K
A
A
M1 1
M2 1
HV_SELECT
2 2
LNB_POWER_ON
SMDMARKT
5
SMDMARKT
4 3 2 1
5
4
3
2
1
D
VINPQ VINNQ VINNI VINPI AGC SCL SDA
VINPQ VINNQ VINNI VINPI AGC SCL SDA
2 2 2 2 2 2 2
Y1 4MHZ_NC C5 22P
C
C6 22P
SA[0..12] SD[0..15] DQML DQMH SDCLK BA0 BA1 SWEN CASN RASN DQML DQMH SDCLK BA0 BA1 SWEN CASN RASN
3 3 3 3 3 3 3 3 3 3
SCL SDA
SCL SDA
SCL SDA
5 5
+3.3V 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VINPQ VINNQ VINNI VINPI R5 TXD RXD SCL SDA DISEQC_OUT CLKOUT CLKIN PANEL_DATA/JTG_TRST_B PANEL_D1/JTG_TMS 100R AGC C2 NC C3 NC C4 NC PANEL_KD/JTG_TDI PANEL_D2/JTG_TDO PANEL_CLK/JTG_TCLK R102 4K7 1 3 5 7 9 11 13 +3.3V
2 2 2 2 R514 4K7 R22 4K7 S_CSJ S_MISO
2Mbyte Serial Flash
C13 R515 4K7 104 1 2 C270 1uF
D
U5 1 2 3 4 CS# SO WP# GND VCC HOLD# SCK SI 8 7 6 5
SA[0..12] SD[0..15] DQML DQMH SDCLK BA0 BA1 SWEN CASN RASN
H1
H2
H3
H4
1
A
1
1 HOLE
1
1 HOLE
1
1 HOLE
1
A
HOLE
5
4
3
2
1
5
4
3
2
1
AUDIO_DAT AUDIO_CLK AUDIO_LRCK
D
AUDIO_DAT AUDIO_CLK AUDIO_LRCK
2 2 2
D
VOUT3
3CVBS/2Y
3CVBS/2Y
2
+3.3V
R106 100R
C
+3.3V L12 FBEAD 1
FLASH&SDRAM +3.3V 34mA~58mA
+3.3V_FLASH_SDRAM
LNB_POWER D11 SS24_SMB 1
VDD=0.5*(1+R1/R2)
BC64 101 1 2 BC65 10uF/25V_1206
2
10uF/25V_1206 2
CPU_CLOCK 0R
R32
R21 CLKIN
1M
VSS33 VDD33 FA18/SIPMISO FA19/GPI027 FWEN FA21/GPI025 FA20/GPI024 FA09 FA10 FA11 FA12 FA13 FA14/SPICSN FA15/SPISCK FA16/SPIMOSI SPDIF/GPI019 PCMSD PCNCLK PCMWS AMCLK/GPI018 VSYNC/GPI022 HSYNC/GPI021 DACREF0 VOUT0 VOUT1 DACREST VOUT2 DACVSSG DACVDDG VOUT3 ADCVDD ADCVSS
AUDIO_DAT AUDIO_CLK AUDIO_LRCK VOUT3 3CVBS/2Y
AUDIO_DAT AUDIO_CLK AUDIO_LRCK 3CVBS/2Y
4 4 4 4
D
CPU_CLOCK VINPQ VINNQ VINNI VINPI AGC DISEQC_OUT DAC_REST 7 HV_SELECT R1 1K R2 200R LNB_POWER_ON
B
B
R3
NC_0R SA12 +3.3V_FLASH_SDRAM
+3.3V_FLASH_SDRAM
SDCLK BA0 BA1
BC14 BC15 BC16 BC17 BC18 BC19 BC20 104 104 104 104 104 104 104
1 2 C271 1uF
A
A
5
4
3
2
1
4Mx16 SDRAM Solution
U6 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 NC NC/RFU VSS VSS VSS VDD VDD VDD VDDq VDDq VDDq VDDq SDRAM_1Mx16x4 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 36 40 28 41 54 1 14 27 3 9 43 49 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
5
4
3
2
1
+12V +12V J2 DC JACK 1 2 3 1 BC46 10uF/25V_1206 BC45 104 BC59 104 R130 BC49 100K 104 BC48 R1206 1 2 3 4 BC50 152 R132 R134 20K 15K NC R135 BC51 152 1 U11 IN NC EN LX COMP GND FB NC G5640(SOP) 8 7 6 5 L26 1 D10 R133 SS24_SMB 2 2 27K NC 104 10uF/25V_1206 10uF/25V_1206 470uF/10V
+3.3V
+3.3V
R129 4K7
R128 4K7
CLKOUT
+1.8V_CORE
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
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