简单计算器一、设计分析1、功能描述设计一个能实现整数0-9之间的简单加、减、乘法运算的计算器，输入和输出均要显示在数码管上。

2、实现工具1、用VHDL 语言文本形式输入；2、maxplusII行语言编写时序仿真和综合。

二、设计思想采用自顶向下的设计方式，分层进行设计。

设计分为五个模块进行；计算器模块、七位二进制数转化成8421BCD码模块，四选一数据选择器模块，七段显示译码器模块、模4计数器模块、2—8译码器块。

顶层设计可以完全独立于目标器件芯片物理结构的硬件描述语言。

使用VHDL模型在所综合级别上对硬件设计进行说明、建模和仿真。

1、顶层原原理框图2、具体实现1、计算器模块2、七位二进制数转化成8421BCD码模块3、四选一数据选择器模块4、七段显示译码器模块5、模4计数器模块6、2—8译码器块三、设计过程1、建立工程建立一个Project，命名为jiandanjisuanqi。

将各个模块生成的文件放在同一个文件夹下。

2、文本输入将各个模块的VHDL代码输入，保存并综合。

3、仿真建立各个模块的gdf图，设置输入波形并仿真。

4、顶层原理图输入利用各个模块生成的sym文件建立顶层原理图，编译并仿真。

5、硬件实现实验室提供的器件为FLEX10K，型号为EPF10K10LC84-4，将文件下载到器件当中，在实验箱中进行模拟。

四、整体框图五、VHDL部分代码及说明1、计算器模块、library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity jisuanqi isPort (a,b: in STD_LOGIC_VECTOR (3 downto 0);sel: in STD_LOGIC_VECTOR (1 downto 0);y: out STD_LOGIC_VECTOR (6 downto 0)); end jisuanqi;architecture rtl of jisuanqi issignal q1 ,q2: STD_LOGIC_VECTOR (3 downto 0);signal q3: STD_LOGIC_VECTOR (1 downto 0);signal q4: STD_LOGIC_VECTOR (6 downto 0);beginq1<=a;q2<=b;q3<=sel;process(q4,q3)begincase q3 iswhen "00" =>q4<=q1+q2;when "01" =>if(q1>q2)thenq4<= q1-q2;elseq4<=q2-q1;end if;when "10"=>q4<=q1*q2;when others=>q4<="0000000";end case;y<=q4;end process;end rtl;2、七位二进制数转化成8421BCD码模块library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity bcd isPort (y : in STD_LOGIC_VECTOR (6 downto 0);a : out STD_LOGIC_VECTOR (3 downto 0);b : out STD_LOGIC_VECTOR (3 downto 0)); end bcd;architecture rtl of bcd issignal q0: STD_LOGIC_VECTOR (6 downto 0);signal q1: STD_LOGIC_VECTOR (3 downto 0);signal q2: STD_LOGIC_VECTOR (3 downto 0);beginprocess(y)beginq0<=y;case q0 iswhen"0000000"=>q1<="0000";q2<="0000";when"0000001"=>q1<="0000";q2<="0001";when"0000010"=>q1<="0000";q2<="0010";when"0000011"=>q1<="0000";q2<="0011";when"0000100"=>q1<="0000";q2<="0100";when"0000101"=>q1<="0000";q2<="0101";when"0000110"=>q1<="0000";q2<="0110";when"0000111"=>q1<="0000";q2<="0111";when"0001000"=>q1<="0000";q2<="1000";when"0001001"=>q1<="0000";q2<="1001";when"0001010"=>q1<="0001";q2<="0000";when"0001011"=>q1<="0001";q2<="0001";when"0001100"=>when"0001101"=>q1<="0001";q2<="0011"; when"0001110"=>q1<="0001";q2<="0100"; when"0001111"=>q1<="0001";q2<="0101"; when"0010000"=>q1<="0001";q2<="0110"; when"0010001"=>q1<="0001";q2<="0111"; when"0010010"=>q1<="0001";q2<="1000"; when"0010011"=>q1<="0001";q2<="1001"; when"0010100"=>q1<="0010";q2<="0000"; when"0010101"=>q1<="0010";q2<="0001"; when"0010110"=>q1<="0010";q2<="0010"; when"0010111"=>q1<="0010";q2<="0011"; when"0011000"=>q1<="0010";q2<="0100"; when"0011001"=>q1<="0010";q2<="0101"; when"0011010"=>q1<="0010";q2<="0110"; when"0011011"=>q1<="0010";q2<="0111"; when"0011100"=>q1<="0010";q2<="1000"; when"0011101"=>q1<="0010";q2<="1001"; when"0011110"=>q1<="0011";q2<="0000"; when"0011111"=>q1<="0011";q2<="0001"; when"0100000"=>q1<="0011";q2<="0010"; when"0100001"=>q1<="0011";q2<="0011"; when"0100010"=>when"0100011"=>q1<="0011";q2<="0101"; when"0100100"=>q1<="0011";q2<="0110"; when"0100101"=>q1<="0011";q2<="0111"; when"0100110"=>q1<="0011";q2<="1000"; when"0100111"=>q1<="0011";q2<="1001"; when"0101000"=>q1<="0100";q2<="0000"; when"0101001"=>q1<="0100";q2<="0001"; when"0101010"=>q1<="0100";q2<="0010"; when"0101011"=>q1<="0100";q2<="0011"; when"0101100"=>q1<="0100";q2<="0100"; when"0101101"=>q1<="0100";q2<="0101"; when"0101110"=>q1<="0100";q2<="0110"; when"0101111"=>q1<="0100";q2<="0111"; when"0110000"=>q1<="0100";q2<="1000"; when"0110001"=>q1<="0100";q2<="1001"; when"0110010"=>q1<="0101";q2<="0000"; when"0110011"=>q1<="0101";q2<="0001"; when"0110100"=>q1<="0101";q2<="0010"; when"0110101"=>q1<="0101";q2<="0011"; when"0110110"=>q1<="0101";q2<="0100"; when"0110111"=>q1<="0101";q2<="0101"; when"0111000"=>when"0111001"=>q1<="0101";q2<="0111"; when"0111010"=>q1<="0101";q2<="1000"; when"0111011"=>q1<="0101";q2<="1001"; when"0111100"=>q1<="0110";q2<="0000"; when"0111101"=>q1<="0110";q2<="0001"; when"0111110"=>q1<="0110";q2<="0010"; when"0111111"=>q1<="0110";q2<="0011"; when"1000000"=>q1<="0110";q2<="0100"; when"1000001"=>q1<="0110";q2<="0101"; when"1000010"=>q1<="0110";q2<="0110"; when"1000011"=>q1<="0110";q2<="0111"; when"1000100"=>q1<="0110";q2<="1000"; when"1000101"=>q1<="0110";q2<="1001"; when"1000110"=>q1<="0111";q2<="0000"; when"1000111"=>q1<="0111";q2<="0001"; when"1001000"=>q1<="0111";q2<="0010"; when"1001001"=>q1<="0111";q2<="0011"; when"1001010"=>q1<="0111";q2<="0100"; when"1001011"=>q1<="0111";q2<="0101"; when"1001100"=>q1<="0111";q2<="0110"; when"1001101"=>q1<="0111";q2<="0111"; when"1001110"=>when"1001111"=>q1<="0111";q2<="1001";when"1010000"=>q1<="1000";q2<="0000";when"1010001"=>q1<="1000";q2<="0001";when others =>q1<="1111";q2<="1111";end case;a<=q1;b<=q2;end process;end rtl;3、四选一数据选择器模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity mux4_1 isport( d0,d1,d2,d3 : in std_logic_vector(3 downto 0);q : out std_logic_vector(3 downto 0);sel : in std_logic_vector(1 downto 0)); end mux4_1;architecture rtl of mux4_1 isbeginprocess(sel)beginif(sel = "00") thenq<=d0;elsif(sel = "01")thenq<=d1;elsif(sel = "10")thenq<=d2;elsif(sel = "11")thenq<=d3;end if;end process;end rtl;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity mux4_1 isport( d0,d1,d2,d3 : in std_logic_vector(3 downto 0);q : out std_logic_vector(3 downto 0);sel : in std_logic_vector(1 downto 0));end mux4_1;architecture rtl of mux4_1 isbeginprocess(sel)beginif(sel = "00") thenq<=d0;elsif(sel = "01")thenq<=d1;elsif(sel = "10")thenq<=d2;elsif(sel = "11")thenq<=d3;end if;end process;end rtl;4、七段显示译码器模块library ieee;use ieee.std_logic_1164.all;entity decode_7 isport( bcdm :in std_logic_vector(3 downto 0);a,b,c,d,e,f,g:out std_logic);end decode_7;architecture rtl of decode_7 issignal w:std_logic_vector(6 downto 0);beginprocess(bcdm)begina<=w(6);b<=w(5);c<=w(4);d<=w(3);e<=w(2);f<=w(1);g<=w(0);case bcdm iswhen "0000"=>w<="1111110";when "0001"=>w<="0110000";when "0010"=>w<="1101101";when "0011"=>w<="1111001";when "0100"=>w<="0110011";when "0101"=>w<="1011011";when "0110"=>w<="1011111";when "0111"=>w<="1110000";when "1000"=>w<="1111111";when "1001"=>w<="1111011";when "1011"=>w<="0000001";when others=>w<="0000000";end case;end process;end rtl;5、模4计数器模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity count_4 isport( clk :in std_logic ;q :out std_logic_vector(1 downto 0)); end count_4;architecture rtl of count_4 issignal qcl : std_logic_vector(1 downto 0);beginprocess(clk)beginif(clk'event and clk = '1')thenif(qcl = "11")thenqcl <= "00";elseqcl <= qcl + '1';end if;end if;q <= qcl;end process;end rtl;6、2—8译码器模块library ieee;use ieee.std_logic_1164.all;entity decode2_8 isport(d :in std_logic_vector(1 downto 0);y :out std_logic_vector(7 downto 0));end decode2_8 ;architecture rt1 of decode2_8 isbeginprocess(d)begincase d iswhen "00"=>y<="10000000";when "01"=>y<="01000000";when "10"=>y<="00100000";when "11"=>y<="00010000";when others=>y<="00000000";end case;end process;end rt1;六、各模块仿真结果1、计算器模块2、七位二进制数转化成8421BCD码模块3.、四选一数据选择器模块4、七段显示译码器模块5、模4计数器模块7、2—8译码器块8、整体仿真七、管脚锁定及硬件实现1、管脚锁定2、文件下载将文件下载完后在硬件实验箱中进行仿真检查。