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集成电路设计CAD_EDA工具实用教程1-Spectre_Verilog数模混合仿真



同时包含模拟和数字两个仿真核
处理速度快,能处理的电路规模极大,但需要解决模拟仿真核和数字 仿真核之间的通信问题;另外,由于数字逻辑仿真器和模拟仿真器的输 入、输出数据是不一样的,还必须在模拟仿真核和数字仿真核之间实现 模拟信号和数字信号的相互转换。
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Q&A
9
Creating Analog Block
3
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高精度模拟/射频电路仿真器

1、Spectre/SpectreRF (Cadence)


2、Hspice/HspiceRF (Synopsys)
3、Ads (Agilent 主要针对RF) 4、Eldo (Mentor Graphics) 5、Saber (Synopsys)
4
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16
Check Block Partition
Change analog & digital stop views to match the stop views in your hierarchy editor (as below)
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17
Check Partition Results
Spectre–Verilog 混合信号仿真
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1
几家EDA软件公司

1、Cadence 2、Synopsys(收购Avanti) 3、Mentor Graphics 4、Silvaco
5、SpringSoft
2
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SPICE仿真器



SPICE : a general-purpose analog circuit simulator developed by the University of California, Berkeley. It is used for nonlinear DC, nonlinear transient, and linear AC analysis. Hspice: a general-purpose circuit simulator from Avanti. It has an extensive set of built-in device models, including models for small geometry MOSFETs and MESFETs. The program is compatible with SPICE input formats. Cadence supports a library of primitives and a full interface for Hspice. Spectre: SPICE-alike analog simulator developed by Cadence.
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5
System in the Real World
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6
Mostly Applied Method of Mixed-Signal Design
系统分成若干个芯片,每个芯片分开设计,再经电路板整合。 或者用SoC实现。
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Integrated Mixed-Signal Design
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数模混合信号仿真器
ห้องสมุดไป่ตู้
1、Spectre-Verilog (Cadence)
2、SMASH (Dolphin Integration) 3、Eldo (Mentor Graphics) 4、Harmony (Silvaco) 5、Saber (Synopsys)
Why MixedSignal Simulation?
Create the schematic view of analog block, and create a symbol view for cell use
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10
Creating Digital Block
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11
Creating a Mixed-Signal Schematic
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14
Open the Schematic Version of Config View
Open the schematic version of the config view of mix from the Library manager
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15
Set Block Partition
开启hierarchy editor 设定所使用的cell view 显示所使用的cell view 及其颜色设定 Schematic editor 中 的Hierarchy-Editor 及Mixed-Signal 两项 Menu是由菜单 Tools->Mixed Signal Opts.而产生的
12
Create Config View for Simulation
The mixed-signal simulation hierarchy is controlled by Hierarchy-Editor which must be defined with config view
cell name is top circuit name for simulation view name will be set as config Use Create New File to create a new config view with Hierarchy-Editor
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8
Mixed-Signal Simulator 的基本结构

以模拟电路仿真器为核心
在处理数模混合电路时将数字部分等效为相应的简化的模拟电路、或 者采用解析函数来表示逻辑模块的行为,然后对整个系统采用模拟电路 的方法进行模拟。优点:模拟结果精确、能处理的电路规模比较大,模 拟速度也有显著提高。缺点:比逻辑模拟器还是慢很多。
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Set New Configuration
1 3. Change the view name to schematic for simulation
3 1.Choose Use Template sample information
2 4. Click OK
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2.Choose spetreVerilog
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