Basic Concepts (基本概念)(P521) Combinational Logic Circuit
（组合逻辑电路）
Outputs Depend Only on its Current Inputs.
(任何时刻的输出仅取决与当时的输入) Character of Circuit: No Feedback Circuit, No Memory Device (电路特点：无反馈回路、无记忆元件)
Figure 7-1
Figure 7-1 (P523)
Why need we the sequential circuit?
串 行 加0 法 器
X0 Y0 X1 Y1
X CI
Y CO
C1
X CI
Y CO
C2
S
S
S0
S1
Xn Yn
XY
CI CO C
S
Sn
思考：能否只用一片1位
XX012 YY012
Chapter 7
Sequential Logic Design Principles
时序逻辑设计原理
(P521)
Chapter 7 Sequential Logic Design Principles
第７章 时序逻辑设计原理
7.1 Bistable Elements 双稳态元件 7.2 latches and Flip-Flops
Basic Concepts (基本概念)
Logic Circuits are Classified into Two Types (逻辑电路分为两大类)：
Combinational Logic Circuit （组合逻辑电路）
Sequential Logic Circuit （时序逻辑电路）
锁存器与触发器
7.3 Clocked Synchronous State- Machine Analysis
同步时钟状态机的分析
7.4 Clocked Synchronous State- Machine Design
同步时钟状态机的设计
Review of Basic Concept
(基本概念回顾)
Logic circuits are classified into two types（逻辑电路分为两大类） combinational logic circuit（组合逻辑电路）
A combinational logic circuit is one whose outputs depend only on its current inputs.（任何时刻的输出仅取决与当时的输入）
characteristic：no feedback circuit sequential logic circuit（时序逻辑电路）
The outputs of a sequential logic circuit depend not only on the current inputs, but also on the past sequence of inputs, possibly arbitrarily far back in time.（任一时刻的输出不仅取决于当时的输入，还取决于过去的输入顺序）
A Clock Signal is Active High if state changes occur at the clock’ Rising Edge of when the clock is High, and Active Low in the complementary case. (时钟信号高电平有效是指在时钟信号的上升沿或时 钟的高电平期间发生变化。反之称时钟信号低电平有 效）
Basic Concepts (基本概念)(P521)
Sequential Logic Circuit
（时序逻辑电路）
Outputs Depend Not Only on its Current Inputs, But also on the Past Sequence of Inputs. (任一时刻的输出不仅取决与当时的输入， 还取决于过去的输入序列)
Character of Circuit: Have Feedback Circuit, Have Memory Device (电路特点：有反馈回路、有记忆元件)
Basic Concepts (基本概念)(P522)
Sequential Logic Circuit
（时序逻辑电路）
Finite-State Machine: Have Finite States. (有限状态机：有有限个状态。）
全加器进行串行加法？？ C012
利用反馈和时钟控制
XY
CI CO
C123
S
反馈
S120
串 行 加0 法 器
X0 Y0 X1 Y1
X CI
Y CO
C1
X CI
Y CO
C1
S
S
S
S
Sn
利用反馈和时钟控制
时钟控制
需要具有记忆功能 的逻辑单元，能够 暂存运算结果。
Clock Frequency: The Reciprocal of the Clock Period. (时钟频率：时钟周期的倒数。）
Basic Concepts (基本概念)(P522)
Sequential Logic Circuit
（时序逻辑电路）
Clock Tick: The First Edge of Pulse in a clock period or sometimes the period itself. (时钟触发沿：时钟周期内的第一个脉冲边沿，或时 钟本身。） Duty Cycle: The Percentage of time that the clock signal is at its asserted level. (占空比：时钟信号有效时间与时钟周期的百分比。）
Basic Concepts (基本概念)(P522) Sequential Logic Circuit
（时序逻辑电路）
Clock Period: The Time between Successive transitions in the same direction. (时钟周期：两次连续同向转换之间的时间。）