PS=PD =105n×2+W
AS=AD =105n×W
重要
90 50
3 50
50
50
55
单位：nm
最小尺寸
W
90
L
50
Poly伸出有源区
50
扩散层伸出poly
105
Poly与有源区间距
50
扩散层与阱边缘间距
55
Contact hole and Via hole (接触孔和通孔)
可获得的Contact hole and Via hole metal1/diff 接触孔 metal1/poly 接触孔 metal1/metal2 通孔 metal2/metal3 通孔
Description Minimum width of poly Minimum spacing of poly AND active Minimum poly extension beyond active Minimum enclosure of active around gate Minimum spacing of field poly to active Minimum Minimum spacing of field poly
Value 70 nm 25 nm 45 nm none
Description Minimum spacing of nimplant/ pimplant to channel Minimum spacing of nimplant/ pimplant to contact Minimum width/ spacing of nimplant/ pimplant Nimplant and pimplant must not overlap
Rule CONTACT.1 CONTACT.2 CONTACT.3 CONTACT.4 CONTACT.5 CONTACT.6 CONTACT.7
Value 65 nm 75 nm none 5 nm 5 nm 35 nm 90 nm
Description Minimum width of contact Minimum spacing of contact saveDerived: contact must be inside active or poly or metal1 Minimum enclosure of active around contact Minimum enclosure of poly around contact Minimum spacing of contact and gate Minimum spacing of contact and poly
层内设计规则
单位：nm
Well
相同阱
0 or 135
200
不同阱
0 or 225
gatepolys fieldpolys
140
75
Poly
50
80
Active
Metal1
65
N+，P+
90
Poly
65
75
con/via1
35
Metal2
70
65
M1 or M2
70
Implant可与well同样大小

35
WEL 135 Minimum spacing of nwell/pwell at L.3 nm the same potential
WEL 200 L.4 nm
Minimum width of nwell/pwell
Rule IMPLANT.1 IMPLANT.2 IMPLANT.3/4 IMPLANT.5
Rule ACTIVE.1 ACTIVE.2 ACTIVE.3 ACTIVE.4
Value 90 nm 80 nm 55 nm none
Description Minimum width of active Minimum spacing of active Minimum enclosure/spacing of nwell/pwell to active saveDerived: active must be inside nwell or pwell
50 140
50
70
50
75
Rule
Valu e
Description
WEL L.1
none
saveDerived: nwell/pwell must not overlap
WEL 225 Minimum spacing of nwell/pwell at L.2 nm different potential
35
重要
最小宽度
Poly
50
metal1
65
有源区（扩散区，N+，P+） 90
Contact or Via Hole
65
最小间距
75/140 65 80 65
2）Inter-Layer Design Rules 层间设计规则
Transistors
70 55
50
50 65 35
90
50
5
单位： nm
设计规则
• lamda规则
– 最小尺寸以lamda的倍数来规定
• 微米规则
– 直接用具体的微米、纳米等单位来规定
• Grid
– 由具体工艺规定 – 分辨率 – 0.18mm工艺为45nm，45nm工艺为2.5nm – 版图中所绘制的矩形、互连线等尺寸必须是它
的倍数
1）Intra-Layer Design Rules
通孔尺寸
Cut(通孔): overlap (复盖) :
65 x 65 5
minimum spacing(间距): 65
diff接触孔与poly间距： 35/90
Rule POLY.1 POLY.2 POLY.3 POLY.4 POLY.5 POLY.6
Value 50 nm 140 nm 50nm 70 nm 50 nm 75 nm
Rule
Value Description
METAL1.1 65 nm Minimum width of metal1
METAL1.2 65 nm Minimum spacing of metal1
NCSU PDK45nm 版图规则
工艺流程
• 与版图的对应关系 • 了解一定的工艺流程背景知识有助于画好
版图
gate-oxide
Tungsten n+
p-well
p-epi p+
TiSi2
AlCu SiO2
poly
n-well
SiO2 p+
VDD
VDD
M2 M4
Vin
Vout
Vout2
M1
M3