2-22
2-22
DV SCHEMATIC DIAGRAM
(12/12) (SERI-PARA)
Line Not connected.
2-23
2-23
2.5 PS250 SCHEMATIC DIAGRAM
Line Not connected.
2-24
2-24
2.6 PS250 CIRCUIT BOARD SIDE A SIDE B
(9/12) (CODEC IF)
Line Not connected.
2-20
2-20
DV SCHEMATIC DIAGRAM
(10/12) (CAM IF)
Line Not connected.
2-21
2-21
DV SCHEMATIC DIAGRAM
(11/12) (HD SDI IF)
Line Not connected.
SD CPU
Flash ROM for FPGA 5/6/7 SD CARD I/O
Line Not connected.
2-18
2-18
DV SCHEMATIC DIAGRAM
(8/12) (MDA IF)
Line Not connected.
2-19
2-19
DV SCHEMATIC DIAGRAM
B-2A B-3A B-3A B-3A B-2A B-2A B-2A B-2A B-2A B-2A B-2A B-2A A-2A A-3A A-3A A-2A A-3A A-3A A-3A B-2A B-2A B-2A B-2A B-2A
R88 R89 R90 R91 R92 R93 R94 R95 R96 R99 R100 R101 R102 R103 R104 R105 R106 R107 R108 R109 R110 R111 R112 R113
(1/12) (FPGA 7)
FPGA 7
Line Not connected.
2-12
2-12
DV SCHEMATIC DIAGRAM
(2/12) (BRIDGE)
MPEG BRIDGE
SDRAM
Line Not connected.
2-13
2-13
DV SCHEMATIC DIAGRAM
(3/12) (DV MAIN)
2-2
2-2
2.3 CAM SCHEMATIC DIAGRAM
(1/9) (IS IF)
Line Not connected.
2-3
2-3
CAM SCHEMATIC DIAGRAM
(2/9) (FPGA 5)
FPGA 5
Line Not connected.
2-4
2-4
CAM SCHEMATIC DIAGRAM
D15 D16 D17 D18 D19 D20 D22 D23 D24 D26 D27 D28 D29 B-2A D30 B-2A D32 B-1A D33 B-2B A-2A R1 A-2A R2 B-2B R3 B-3B R4 A-2B R10 B-2B R12 B-2B R13 B-3B B-2B B-2B A-3A A-3A B-2B B-2B B-3A B-2A B-3A A-1A B-1B
B
B
A
A
1
2
3
3
2
1
ADDRESS TABLE OF BOARD PARTS Each address may have an address error by one interval. A-1C Side Y axis X axis
IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC10 IC11 IC13 IC14 IC15 Q1 Q2 Q3 Q4 Q6 Q7 Q8 Q9 Q10 Q11
B-2B B-3A B-3A B-3B B-3B B-2B A-1A B-1A A-1A A-1B A-1B B-1B B-1B B-1B B-3B A-1A B-2A B-2A B-2A B-2A B-2A B-2B A-2B
R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R37 R38
ANALOG IF
Line Not connected.
2-7
2-7
CAM SCHEMATIC DIAGRAM
(6/9) (JCS0054)
Aed.
2-8
2-8
CAM SCHEMATIC DIAGRAM
(7/9) (CLK BLOCK)
Line Not connected.
B-1A A-1B A-2B A-1B A-1B A-1A A-2B B-2B B-2B B-3B B-1A B-1A B-1A A-3B A-2B B-1A A-1A A-2B A-2B A-3A B-1B
CN29 CN30 CN75 CN88 CN91 CN92 CN93 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K16 K17
A-3A A-2A A-2A A-2A A-2A B-1B A-3B A-3B A-3B A-3A B-2A B-3A B-2A B-3A B-2A B-2A B-2A B-2A B-2A B-2A B-2A B-2A B-2A A-2A
C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72 C73 C74 C76 C77 C78
2-9
2-9
CAM SCHEMATIC DIAGRAM
(8/9) (CAM CPU)
CAM CPU
Line Not connected.
2-10
2-10
CAM SCHEMATIC DIAGRAM
(9/9) (B TO POW)
Line Not connected.
2-11
2-11
2.4 DV SCHEMATIC DIAGRAM
B-2B B-2B B-3B A-3B A-3B B-3B A-3B A-2A B-2B B-2B A-2B A-2B B-2B B-2B B-2B B-2B B-2B B-3A A-3A B-3A A-3A B-2B B-2A B-3A
C79 C80 C81 C82 C83 C85 C86 C87 C88 C89 C91 C94 C96 C97 C100 C101 C102 C103 C104 C105 C106 C107 C108 C109
A-2B A-1B A-2B B-2A B-2A B-2A B-1A B-2A B-2A B-2A B-1A B-1A B-2A B-1A B-1A B-2B B-2B B-3B B-1A B-1B B-3B A-1A B-2A B-3A
C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25
MSD CPU
Line Not connected.
2-16
2-16
DV SCHEMATIC DIAGRAM
(6/12) (SYS CPU)
EEP-ROM
SYS CPU RTC
Line Not connected.
2-17
2-17
DV SCHEMATIC DIAGRAM
(7/12) (SD CPU)
SECTION 2 DIAGRAMS AND CIRCUIT BOARDS
2.1 OVERALL WIRING DIAGRAM 1/2 (GY-HD200(A) STEP-1)
NC
2-1
2-1
2.2 OVERALL WIRING DIAGRAM 2/2 (GY-DH200(A) STEP-2)
NC
(3/9) (ASIC)
CAM PROCESS
108M BUS
Line Not connected.
2-5
2-5
CAM SCHEMATIC DIAGRAM
(4/9) (FPGA 6)
PIX CONV.
Line Not connected.
2-6
2-6
CAM SCHEMATIC DIAGRAM
(5/9) (JCP8076)
A-2B B-1B B-2B B-2B B-1B B-2B B-2B B-2B B-2B B-2B B-2B A-2A A-2A A-2A A-2A A-2A A-2A A-2A A-2A A-2A A-2A A-2A A-3A A-3A
R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62
B-1B B-2A B-1B B-2B A-2A B-2A A-3B A-2A B-1A A-1B A-1A A-1B B-1B B-2A B-2A B-2B B-2A B-1B B-2B B-2B B-2B A-2A B-3B
Q12 Q14 Q15 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q25 D1 D2 D3 D6 D7 D8 D10 D11 D12 D13 D14
A-3B B-2B B-2A B-2A B-3A B-3A B-3A B-2A B-3A B-3A B-2A B-3B B-2A B-3A B-3A B-3A B-3A B-3A B-3A B-3A B-2A B-2A B-3A B-3A