生命科学技术学院《CMOS专用集成电路》实验报告学院（系）：生命科学技术学院专业：生物医学工程班级：151011学号：15101004学生姓名：柳琳2013年06 月29 日一、实验题目（1）更改测试文件相关部分的参数值，将该乘法器的数据位宽改为8-Bit。

（2）根据对实验电路的分析，绘制该移位式乘法器电路详细的电路结构框图，并对每一功能部件的功能及相关参数的意义进行说明；（3）采用Verilog HDL硬件描述语言设计一个16-Bit超前进位加法器；（4）在上面超前进位加法器基础上，将原电路的部分积求和电路改进成超前进位加法器。

二、实验结果与讨论（1）更改测试文件相关部分的参数值，将该乘法器的数据位宽改为8-Bit。

module multiplier_nbit ( rst, clk, x, y, result );parameter mwidth = 8;parameter rwidth = mwidth + mwidth;input rst, clk;…reg [1:0] stcnt;reg [2:0] mucnt;…assign mucnt_en = (stcnt == 2'b01) ? 1'b1 : 1'b0;assign mucnt_full = (mucnt == 3'b111) ? 1'b1 : 1'b0;assign stcnt_load = (stcnt == 2'b10) ? 1'b1 : 1'b0;…always @(posedge rst or posedge clk)beginif(rst)mucnt <= 3'b000;else if(mucnt_en)mucnt <= mucnt + 1;elsemucnt <= mucnt;endmodule test_mult;reg rst, clk;reg [7:0] x, y;wire [15:0] result;initialbeginclk = 1'b0;rst = 1'b0;#25 rst = 1'b1;x = 16'h01;y = 16'h02;#25 rst = 1'b0;#160 x = 16'h02;y = 16'h03;#160 x = 16'h01;y = 16'h02;#160 x = 16'h03;y = 16'h04;#160 x = 16'h05;y = 16'h06;endmodule adder_nbit(a, b, sum, co);parameter width = 8;input [width-1:0] a, b;output [width-1:0] sum;wire [width-1:0] sum;output co;wire co;wire [width-1:0] sum_mag;wire auxc_bit, sign_bit;assign sum_mag = {1'b0, a[width-2:0]} + {1'b0, b[width-2:0]};assign auxc_bit = sum_mag[width-1];assign sign_bit = a[width-1] ^ b[width-1] ^ auxc_bit;assign co = (a[width-1] & b[width-1]) | (a[width-1] & auxc_bit) | (b[width-1] & auxc_bit);assign sum = {sign_bit, sum_mag[width-2:0]};endmoduleFigure 1乘法器（2）根据对实验电路的分析，绘制该移位式乘法器电路详细的电路结构框图，并对每一功能部件的功能及相关参数的意义进行说明；（3）采用Verilog HDL硬件描述语言设计一个16-Bit超前进位加法器；（未完成）（4）在上面超前进位加法器基础上，将原电路的部分积求和电路改进成超前进位加法器。

（未完成）四、实验心得与意见反馈通过两次CMOS专用集成电路的上机，我了解了verilog语言的结构，并学会了Modelsim 仿真软件的初步使用。

学会了用modelsim软件对设计的电路进行仿真，通过修改变量了解到电路如何控制小灯的闪烁。

希望增加上机次数五、附程序源代码1、实用型移位式乘法器电路描述：//******************************************************************////****** MODULE DESCRIPTION : 16-Bit Practical Shift Multiplier//****** AUTHOR : rzH//****** DATE : 06.20.2013//******************************************************************//module multiplier_nbit ( rst, clk, x, y, result );//data width definitionparameter mwidth = 16;parameter rwidth = mwidth + mwidth;//input rst, clk;//input operation data x and yinput [mwidth-1:0] x, y;//output multiply resultoutput [rwidth-1:0] result;reg [rwidth-1:0] result;//stcnt: state counter---3 state//state 0: input data registered//state 1: multiply operation//state 2: output data registeredreg [1:0] stcnt;//mucnt: multiply step counter---16 stepreg [3:0] mucnt;//multiplicand registerreg [mwidth-1:0] opx;//partial product register//also to save resource, multiplier are initially//stored in the low 16bit of the registerreg [rwidth-1:0] ptpro;//select data source to multiplicand registerwire tx_sel;//select data source to partial product registerwire [1:0] tp_sel;//select data source to ptadd according to//the lowest bit of the multiplier in multiply processwire adp_sel;wire [rwidth-1:0] ptshf1, ptshf0, ptadd;//partial product initialwire [rwidth-1:0] ptini;//temprorywire [mwidth-1:0] temp_x;reg [rwidth-1:0] temp_p;//output multiply result enablewire mout_en;//16-bit adder output: summary and carrywire [mwidth-1:0] sum;wire co;//stcnt state 1: start multiply processassign mucnt_en = (stcnt == 2'b01) ? 1'b1 : 1'b0;//multiply process endassign mucnt_full = (mucnt == 4'b1111) ? 1'b1 : 1'b0;//stcnt state end and load initial stateassign stcnt_load = (stcnt == 2'b10) ? 1'b1 : 1'b0;//stcnt count enableassign stcnt_en = ((!mucnt_en) || mucnt_full) ? 1'b1 : 1'b0; always @(posedge rst or posedge clk)beginif(rst)stcnt = 2'b00;else if(stcnt_load)stcnt = 2'b00;else if(stcnt_en)stcnt = stcnt + 1;elsestcnt = stcnt;endalways @(posedge rst or posedge clk)beginif(rst)mucnt <= 4'b0000;else if(mucnt_en)mucnt <= mucnt + 1;elsemucnt <= mucnt;end//select initial or intermediate resultassign tx_sel = (stcnt == 2'b00) ? 1'b1 : 1'b0;assign temp_x = tx_sel ? x : opx;assign tp_sel = stcnt;assign ptini = {{mwidth{1'b0}}, y};assign adp_sel = (ptpro[0] == 1'b1) ? 1'b1 : 1'b0;//the lowest bit of the multiplier is 1assign ptshf1 = {co, sum, ptpro[mwidth-1:0]} >> 1;//the lowest bit of the multiplier is 0assign ptshf0 = ptpro >> 1;assign ptadd = adp_sel ? ptshf1 : ptshf0;//select initial or intermediate resultalways @(tp_sel or ptini or ptadd or ptpro)begincase(tp_sel)2'b00: temp_p = ptini;2'b01: temp_p = ptadd;2'b10: temp_p = ptpro;default: temp_p = ptpro;endcaseend//register multiplicand and partial productalways @(posedge rst or posedge clk)beginif(rst)beginopx <= {mwidth{1'b0}};ptpro <= {rwidth{1'b0}};endelsebeginopx <= temp_x;ptpro <= temp_p;endend//output multiply resultassign mout_en = (stcnt == 2'b10) ? 1'b1 : 1'b0;always @(posedge rst or posedge clk)beginif(rst)result <= {rwidth{1'b0}};else if(mout_en)result <= ptpro;elseresult <= result;end//adder_nbit u0(.a(ptpro[rwidth-1:mwidth]), .b(opx), .sum(sum), .co(co));endmodule2、测试向量设计：module test_mult;reg rst, clk;reg [15:0] x, y;wire [31:0] result;initialbeginclk = 1'b0;rst = 1'b0;#25 rst = 1'b1;x = 16'h0000;y = 16'h0003;#25 rst = 1'b0;#160 x = 16'h0012;y = 16'h0013;#160 x = 16'h0134;y = 16'h0213;#160 x = 16'h1234;y = 16'h2587;#160 x = 16'hffff;y = 16'hffff;endalways #5 clk = ~clk;multiplier_nbit u0(.rst(rst), .clk(clk), .x(x), .y(y), .result(result)); endmodule。