• Channel-wise programmable sampling time • External Analog Input Channels for each of the 3 ADCs:
• • 5 fast channels from dedicated GPIOs pads Up to 11 slow channels from dedicated GPIOs pads
2
• Programmable Conversion resolution : 12, 10, 8 or 6 bit • Low power design
• • Consumption linear vs. conversion rate : 200 µA / MSps ADC speed independent from CPU frequency (dual clock architecture)
Presentation Title
02/07/2015
ADC Deep-Power-Down Mode
• By default, the ADC is placed in deep-power-down mode where its supply is internally switched off to reduce the leakage currents, • To start ADC operations the following sequence should be applied:
AWD2_OUT
JEXTI15 JEXTSEL[3:0] bits
ADC interrupt to NVIC TIMERs
Presentation Title
02/07/2015
AWD1_OUT
AWD3_OUT
. . . . . . . . . .
AREADYIE EOSMPIE
EOCIE
EOSIE OVRIE JEOSIE JQOVFIE AWDxIE
4
Remarks
The higher/positive reference voltage for the ADC, 2.0V ≤ VREF+ ≤ VDDA if VDDA ≥ 2V, VREF+ = VDDA if VDDA < 2.0V Analog power supply independent from VDD and 1.62 V ≤ VDDA ≤ 3.6V The lower/negative reference voltage for the ADC, VREF- = VSSA Ground for analog power supply equal to VSS Connected either to external channels: ADC_INi or internal channels. Connected to VREF- or external channels: ADC_INi-1 Up to 16 analog input channels (x=ADC number = 1,2,3): • 5 fast channels • 11 slow channels
• Can manage Single-ended or differential inputs • Self-calibration
02/07/2015 Presentation Title
ADC Features (2/2)
• 5 internal channels connected to :
• • • • Temperature sensor Vsense connected to ADC1 and ADC3 Internal voltage reference VREFINT connected to ADC1 VBAT/3 power supply connected to ADC1 and ADC3 DAC1_int, DAC2_int connected to ADC2
ADC Startup
ADC Calibration
OFF Request
Note: The calibration factor is lost when entering Standby, Shutdown, Vbat mode or when the ADC enter deep power down mode. In this case it is possible to re-write the calibration factor into the ADC_CALFACT register without recalibrating.
Reset & Clock controller
/1 , /2 or /4
ADC123_CK
/1 … /256
Analog ADC3 (single)
Presentation Title
02/07/2015
How to choose ADC Clock
ADC clock source Benefits
8
DEEPPWD ADVREGEN TADCVREG_STUP ADC Calibration
ADC Calibration process
ADC state
ADC OFF
By Software
ADC calibration
ADC OFF
Presentation Title
02/07/2015
ADC Calibration
AUTDLY
Start & Stop
3 Analog watchdog
ADSTP
Control
S/W trigger
EXTI0 EXTI1
AREADY EOSMP
H/W trigger
EOC
EOS
OVR JEOS JQOVF AWDx
Analog Watchdog
EXTI15 EXTSEL[3:0] bits JEXTI0 JEXTI1 J S/W trigger
9
ADCALDIF
0 : SINGLE ENDED INPUT
1 : DIFFERENTIAL INPUT
ADCAL ADC state OFF
startup
ADC Calibration
OFF
CALFACT_x[6:0]
0x00
Calibration factor
By Software
By Hardware
Drawbacks
Clock constraints when using injected channels
Uncertainty of the trig instant is added by the resynchronizations between the two clock domains
• The calibration factor to be applied for single-ended input conversions is different from the factor to be applied for differential input conversions:
High Threshold register (12bits)
Low Threshold register (12bits)
ADC Clocks
ADC1, ADC2 & ADC36Hຫໍສະໝຸດ LKAHB interface
Analog ADC1 (master) Analog ADC2 (slave)
CKMODE[0:1]
STM32L4 Analog Peripheral
Analog-to-digital converter (ADC)
ADC Features (1/2)
• Up to 3 ADCs:
• • ADC1 & ADC2 are tightly coupled and can operate in dual mode (ADC1 is master) ADC3 is standalone, but it share the interface with ADC1 & 2
7
ADC123_CK
Independent and asynchronous ADC clock versus AHB clock
AHB div 1, 2 or 4
Bypassing the clock domain resynchronizations: deterministic latency between the trigger event and the start of conversion
5
DMA Request
oversampler
ANALOG MUX
Address/data bus
SAR ADC
Sample and hold Start
12bits
Injected data register (4x16bits) Regular data register (16bits)
12bits
02/07/2015 Presentation Title
ADC Pins
Name VREF+ Signal Type
Input, analog reference positive Input, analog supply Input, analog reference negative Input, analog supply ground Positive input analog channels for each ADC Negative input analog channels for each ADC External analog input signals