fpga设计电子时钟（12864显示）设计心得：1，进行分块设计，类似调用函数，脉冲使能2，充分了解fpga的并行特性（c程序的串行特性，不能并行处理，线性：只有完成了当前任务，才能进行下一个任务）设计问题：1，似乎读有问题，在char_LR=1时，写的数据为汉字（程序中时间没有更改，主要为了调试看波形）实际板子验证时，将LCD_clk模块中的分频调为50到100kHz左右整体架构液晶初始化时序parameter Idle =8'b0000_0001,Basic_ =8'b0000_0010, //basic instruction:0x30Disp_set =8'b0000_0100, //set show curse blingDDRAM_clear =8'b0000_1000, //colunm address XWait_clear =8'b0001_0000,Point_set =8'b0010_0000,Show_on =8'b0100_0000,Stop=8'b1000_0000;写字符的时序由于字符属于半宽字形，且DDRAM形式下，每行只有8个地址，而字符可以写16个，因此用下面三个来表示写的地址：i nput [1:0] Y, //row 0-3i nput [2:0] X, //clunm 0-7i nput LR, //0/1因此当LR=0时，直接写地址，然后写一个字符编码即可LR=1时，先写地址，读出高位数据，然后写入两个字节（读出的数据，要写的数据）parameter Idle =8'b0000_0001,DDRAM =8'b0000_0010, //drawing modeW_addr =8'b0000_0100, //row address YDummy =8'b0000_1000, // not really readingR_data =8'b0001_0000, //reading high byte dataW0_data =8'b0010_0000,W1_data =8'b0100_0000,Stop =8'b1000_0000;# t1: 0 t2: 2305, T: 10,n_init: 38 # t1: 2305 t2: 2665, T: 10,n_char: 6 # t1: 2665 t2: 3265, T: 10,n_char: 10完成了上述工作，就可以设计一个简单的电子时钟，其要求如下：在屏幕上显示时间00：00：00要动态走（主要就是控制脉冲信号的产生）设计思路：1，按下复位键，系统复位，时间变为00：00：002，每一秒中时分秒数据更改3，一秒钟时间到，产生8个字符写的脉冲，LCD更新数据显示00:00:0100:01:591代码/*sign.v//creat the control signclock h:m:s*/module sign(//module LED(input lcd_clk, //100kHzinput sys_rst,output reg lcd_char_en,output reg lcd_init_en,output reg [7:0]char_data,output reg [2:0]char_X,output reg [1:0]char_Y,output reg char_LR);parameter T_w_char = 5,T_lcd_init = 40;reg [47:0] time_out;/* 1s */reg [16:0] t_s;reg [5:0] t0_clk;reg [3:0] t1_clk;reg [2:0] t_char;reg [5:0] sec,min;reg [4:0] hour;reg flag_s,flag_init;always @ (posedge lcd_clk or negedge sys_rst) begin //100kHz if(!sys_rst)begint_s <=0;t0_clk<=0;t1_clk<=0;t_char<=0;sec <=0;min <=0;hour <=0;flag_s <=0;flag_init <=1'b1;char_Y <= 2'b10;endelsebeginif(t_s == (40-1))begint_s <=0;flag_s<=1'b1;data_deal; //taskendelset_s <=t_s+1'b1;if(flag_init)begint0_clk <= t0_clk +1'b1;case(t0_clk)1 : begin lcd_init_en <=1'b0; end2 : begin lcd_init_en <=1'b1; end3 : begin lcd_init_en <=1'b1; end4 : begin lcd_init_en <=1'b0; endT_lcd_init: beginflag_init <=0;t0_clk <=0;enddefault: lcd_init_en <=0;endcaseendelseif(flag_s)begint1_clk <= t1_clk +1'b1;case(t1_clk)1 : begin lcd_char_en <=1'b0; e nd2 : begin lcd_char_en <=1'b1; e nd3 : begin lcd_char_en <=1'b1; e nd4 : begin lcd_char_en <=1'b0; e ndT_w_char: beginif(t_char == 3'b111)begin t_char<=0; flag_s <=0; endelset_char <=t_char+1'b1;t1_clk <=0;enddefault: lcd_char_en <=0;endcasecase(t_char)//2 3 4 50 : begin char_X <=3'b000; char_LR <=0; char_data <=time_out[47:40]; end //x0:00:001 : begin char_X <=3'b001; char_LR <=0; char_data <=time_out[39:32]; end //0x:00:002 : begin char_X <=3'b010; char_LR <=0; char_data <=8'h3a; end //: ascii 0583 : begin char_X <=3'b011; char_LR <=0; char_data <=time_out[31:24]; end //00:x0:004 : begin char_X <=3'b100; char_LR <=0; char_data <=time_out[23:16]; end //00:0x:005 : begin char_X <=3'b101; char_LR <=0; char_data <=8'h3a; end //: ascii 0586 : begin char_X <=3'b110; char_LR <=0; char_data <=time_out[15: 8]; end//00:00:x07 : begin char_X <=3'b111; char_LR <=0; char_data <=time_out[7 : 0]; endendcaseendendendtask data_deal;beginif(sec == 59)if(min ==59)if(hour == 23)begin hour<=0;min <=0;sec <=0; endelsebegin hour<=hour + 1'b1; min <=0; sec<=0; endelsebegin min <= min+1'b1; sec <=0; endelsesec <= sec +1'b1;time_out[47:40] <= 8'h30+(hour/10);time_out[39:32] <= 8'h30+(hour%10);time_out[31:24] <= 8'h30+(min /10);time_out[23:16] <= 8'h30+(min %10);time_out[15: 8] <= 8'h30+(sec /10);time_out[ 7: 0] <= 8'h30+(sec %10);endendtaskendmodule2代码module LCD_init(//module LED(input lcd_clk,input sys_clk,input lcd_en, //1 is activedoutput reg LCD_RS,output reg LCD_RW,output reg LCD_EN,inout [7:0] LCD_DATA,output reg ACK);reg flag;reg [7:0] lcd_data;reg [7:0] State;reg link_rs;reg link_data;parameter Idle =8'b0000_0001,Basic_ =8'b0000_0010, //basic instruction:0x30Disp_set =8'b0000_0100, //set show curse blingDDRAM_clear =8'b0000_1000, //colunm address XWait_clear =8'b0001_0000,Point_set =8'b0010_0000,Show_on =8'b0100_0000,Stop =8'b1000_0000;reg [9:0] t; //16*2*32=2^10 byte(8bits)/* LCD_RW LCD_DATA*/assign LCD_DATA = link_data ? lcd_data: 8'hzz;/* LCD_RW LCD_EN */always @ (posedge sys_clk) beginif(flag)beginLCD_RW =0;LCD_EN = lcd_clk;endelsebeginLCD_RW =1'bz;LCD_EN =1'bz;endend/* LCD_RS */always @ (posedge lcd_clk) beginif(link_rs)LCD_RS <=1'b0;elseLCD_RS <=1'bz;end/*-Main state transter-*/always @ (posedge lcd_clk) begincase (State)Idle : beginif(lcd_en)begin link_rs=1; State <= Basic_; endelseState <= Idle;ACK =0;flag <=1'b0;lcd_data <= 8'hzz;t <= 0;endBasic_ : beginflag <=1'b1;link_data =1'b1;t <= t +1'b1;if(t == 1)State <= Disp_set;elseState <= Basic_;lcd_data <= 8'h30;endDisp_set : beginState <= DDRAM_clear;lcd_data <= 8'h0c; //show curse blink is offendDDRAM_clear : beginState <= Wait_clear;lcd_data <= 8'h01;endWait_clear : begint <=t +1'b1;link_data = 1'b0;flag <=0;lcd_data <= 8'hzz;if(t == 30)State <= Point_set;elseState <= Wait_clear;endPoint_set : beginflag <=1'b1;link_data =1'b1;State <= Show_on;lcd_data <= 8'h06; //point +1 automatically,screen move off endShow_on : beginState <= Stop;lcd_data <= 8'h0c;endStop : beginState <= Idle;flag <=1'b0;link_data =1'b0;ACK <=1'b1;lcd_data <= 8'hzz;t <= 0;link_rs =0;enddefault: begin ACK =0;State <= Idle;end endcaseendendmodule3代码//module LCD_top(module LED(input sys_clk,input sys_rst,output LCD_RS,output LCD_RW,output LCD_EN,inout [7:0] LCD_DATA,output BUSY);wire [7:0] char_data;wire [2:0] char_X;wire [1:0] char_Y;sign singb(.lcd_clk (lcd_clk), //100kHz.sys_rst (sys_rst),.lcd_char_en(lcd_char_en),.lcd_init_en(lcd_init_en),.char_data (char_data),.char_X (char_X),.char_Y (char_Y),.char_LR (char_LR));LCD_init lcd_init(.lcd_clk (lcd_clk),.sys_clk (sys_clk),.lcd_en (lcd_init_en), //1 is actived .LCD_RS (LCD_RS),.LCD_RW (LCD_RW),.LCD_EN (LCD_EN),.LCD_DATA (LCD_DATA),.ACK (init_ack));LCD_charac a(.lcd_clk (lcd_clk),.sys_clk (sys_clk),.lcd_en (lcd_char_en), //1 is actived .Y (char_Y), //row 0-3.X (char_X), //clunm 0-7.LR (char_LR), //0/1.data_disp (char_data),.LCD_RS (LCD_RS),.LCD_RW (LCD_RW),.LCD_EN (LCD_EN),.LCD_DATA (LCD_DATA),.ACK (init_ack));LCD_clk clk1(.sys_clk (sys_clk),.lcd_clk (lcd_clk));endmodule4代码module LCD_clk(//module LED(input sys_clk,output reg lcd_clk);/*-creat the 25kHz clock-*/always @ (posedge sys_clk) beginif(lcd_t == 2) //100kHzbeginlcd_t =0;lcd_clk <= ~ lcd_clk;endelselcd_t = lcd_t +1'b1;endinitial begin lcd_clk =0; lcd_t =0; endendmodule5代码/* to display character */module LCD_charac(//module LED(input lcd_clk,input sys_clk,input lcd_en, //1 is activedinput [1:0] Y, //row 0-3input [2:0] X, //clunm 0-7input LR, //0/1input [7:0] data_disp,output reg LCD_RS,output reg LCD_RW,output reg LCD_EN,inout [7:0] LCD_DATA,output reg ACK);reg [7:0] lcd_data;reg [7:0] R_buff;reg [7:0] State;parameter Idle =8'b0000_0001,DDRAM =8'b0000_0010, //drawing modeW_addr =8'b0000_0100, //row address YDummy =8'b0000_1000, // not really readingR_data =8'b0001_0000, //reading high byte dataW0_data =8'b0010_0000,W1_data =8'b0100_0000,Stop =8'b1000_0000;reg flag,t;reg flag0;/* LCD_DATA */assign LCD_DATA = link_data ? lcd_data :8'hzz;/* LCD_EN */always @ (posedge sys_clk) beginif(flag == 1'b1)LCD_EN <= lcd_clk;elseLCD_EN <=1'bz;end/* LCD_RW */always @ (posedge lcd_clk) beginif(flag0)if(State == Dummy || State == R_data)LCD_RW <=1'b1;elseLCD_RW <=1'b0;elseLCD_RW <=1'bz;end/* LCD_RS */always @ (posedge lcd_clk) beginif(flag0)if(State == W0_data || State == W1_data || State == Dummy || State == R_data) LCD_RS <=1'b1;elseLCD_RS <=1'b0;elseLCD_RS <=1'bz;end/*-Main state transter-*/always @ (posedge lcd_clk) begincase (State)Idle : beginif(lcd_en)begin State <= DDRAM; link_data =1; flag0=1'b1; endelsebegin State <= Idle; flag0= 1'b0;endflag <= 1'b0;lcd_data <= 8'hzz;ACK <=0;endDDRAM : begin //here flag is changed,not Idle, cause sys_clk flag <= 1'b1;State <= W_addr;link_data =1;lcd_data <= 8'h30;endW_addr : beginif(!t)beginif(LR)State <= Dummy;elseState <= W0_data;t =1'b1;endelseState <= W0_data;case (Y)2'b00: lcd_data <= 8'h80 + X;2'b01: lcd_data <= 8'h90 + X;2'b10: lcd_data <= 8'h88 + X;2'b11: lcd_data <= 8'h98 + X;endcaselink_data =1'b1;endDummy : beginState <= R_data;R_buff <= LCD_DATA;link_data =0;endR_data : beginState <=W_addr;R_buff <= LCD_DATA;endW0_data : beginif( !LR)beginlcd_data <= data_disp;State <= Stop;endelsebeginlcd_data <= R_buff;State <= W1_data;endendW1_data : beginlcd_data <= data_disp;State <=Stop;flag0=0;endStop : beginState <= Idle;flag <= 1'b0;lcd_data <= 8'hzz;t <= 0;ACK <= 1;enddefault: begin ACK =0;State <= Idle; link_data=0 ;end endcaseendendmodule。