数字电路与逻辑设计实验报告学院：电子工程学院班级：姓名：学号：班内序号：目录（一）实验名称及实验任务要求 (1)（二）模块端口说明及连接图 (2)1.1实验三(3)模块端口说明 (2)1.2实验三(3)连接图 (2)2.1实验四模块端口说明 (2)2.2实验四连接图 (2)（三）原理图或VHDL代码 (3)1.实验一(2)原理图 (3)2.实验三(3)VHDL代码 (4)3.实验四VHDL代码 (7)（四）仿真波形 (10)1.实验一(2)仿真波形 (10)2.实验三(3)仿真波形 (11)3.实验四仿真波形 (11)（五）仿真波形分析 (11)1.实验一(2)仿真波形分析 (11)2.实验三(3)仿真波形分析 (11)3.实验四仿真波形分析 (11)（六）故障及问题分析 (12)（七）总结和结论 (13)（一）实验名称及实验任务要求实验一名称：QuartusII原理图输入法设计与实现实验任务要求：EDA基础实验1（1）、（2）、（3）必做，选做VHDL 实现加法器。

实验二名称：用VHDL设计与实现组合逻辑电路实验任务要求：四人表决器、8421码转格雷码、数码管译码器（下载测试）。

实验三名称：用VHDL设计与实现时序逻辑电路实验任务要求：分频器、8421十进制计数器、将分频器/8421十进制计数器/数码管译码器3个电路进行连接并下载。

实验四名称：用VHDL设计与实现相关电路实验任务要求：数码管动态扫描控制器、点阵扫描控制器。

（二）模块端口说明及连接图1.1实验三(3)模块端口说明cp：时钟信号输入；rst：8421十进制计数器异步置位；c[6...0]：七段二极管数码管显示；cat[7...0]：数码管显示。

1.2实验三(3)连接图2.1实验四模块端口说明cp：时钟信号输入；rst：8421计数器异步复位；lgt[6...0]：七段二极管数码管显示；cat[7...0]：数码管显示。

2.2实验四连接图（三）原理图或VHDL代码1.实验一(2)原理图半加器：全加器：2.实验三(3)VHDL代码//分频器部分library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all; entity div_12 isport(cp: in std_logic;clk1: out std_logic);end div_12;architecture a of div_12 issignal tmp: integer range 0 to 11;beginprocess (cp)beginif (cp'event and cp='1') thenif tmp=11 then tmp<=0;else tmp<=tmp+1;end if;if tmp<=5 then clk1<='0';else clk1<='1';end if;end if;end process;end a;//8421十进制加法器部分library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity jisuqi8421 isport(clk2,rst: in std_logic;q: out std_logic_vector(3 downto 0));end jisuqi8421;architecture a of jisuqi8421 issignal q_temp:std_logic_vector (3 downto 0); beginprocess(clk2,rst)beginif (rst='1') thenq_temp<="0000";elsif (clk2'event and clk2='1') thenif q_temp>="1001" then q_temp<="0000";elseq_temp<=q_temp+1;end if;end if;end process;q<=q_temp;end a;//译码管部分LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY yimaguan ISPORT(a: IN STD_LOGIC_VECTOR (3 downto 0);b: OUT STD_LOGIC_VECTOR (6 downto 0);cat: out std_logic_vector(7 downto 0));end yimaguan;ARCHITECTURE seg7_1_arch OF yimaguan ISBEGINPROCESS(a)BEGINCASE a ISWHEN"0000" => b <="1111110"; --0WHEN"0001" => b <="0110000"; --1WHEN"0010" => b <="1101101"; --2WHEN"0011" => b <="1111001"; --3WHEN"0100" => b <="0110011"; --4WHEN"0101" => b <="1011011"; --5WHEN"0110" => b <="1011111"; --6WHEN"0111" => b <="1110000"; --7WHEN"1000" => b <="1111111"; --8WHEN"1001" => b <="1111011"; --9WHEN OTHERS => b <="0000000";END CASE;END PROCESS;cat<="11101111";END;//整体显示library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity display isport(cp,rst: in std_logic;c:out std_logic_vector(6 downto 0);cat: out std_logic_vector(7 downto 0));end display;architecture r of display iscomponent div_12port(cp:in std_logic;clk1:out std_logic);end component;component jisuqi8421port(clk2,rst:in std_logic;q:out std_logic_vector(3 downto 0));end component;component yimaguanport(a:in std_logic_vector(3 downto 0);b:out std_logic_vector(6 downto 0);cat: out std_logic_vector(7 downto 0));end component;signal x:std_logic;signal y:std_logic_vector(3 downto 0);beginu1:div_12 port map(cp=>cp,clk1=>x);u2:jisuqi8421 port map(clk2=>x,rst=>rst,q=>y); u3:yimaguan port map(a=>y,b=>c,cat=>cat); end r;3.实验四VHDL代码//分频器分频部分library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity div isport(cp: in std_logic;clk1: out std_logic);end div;architecture a of div issignal tmp: integer range 0 to 49;beginprocess (cp)beginif (cp'event and cp='1') thenif tmp=49 then tmp<=0;else tmp<=tmp+1;end if;if tmp<=25 then clk1<='0';else clk1<='1';end if;end if;end process;end a;//计数器计数部分library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity count isport(clk,rst: in std_logic;q: out std_logic_vector(3 downto 0));end count;architecture a of count issignal temp:std_logic_vector (3 downto 0); beginprocess(clk,rst)beginif (rst='1') thentemp<="0000";elsif (clk'event and clk='1') thenif temp>="0101" then temp<="0000";elsetemp<=temp+1;end if;end if;end process;q<=temp;end a;//译码管显示部分library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity yimaqi isport(a:in std_logic_vector(3 downto 0);led:out std_logic_vector(6 downto 0);cat:out std_logic_vector(7 downto 0));end entity;architecture rtl of yimaqi isbeginprocess(a)begincase a iswhen "0000"=>led<="1111110"; cat<="11111110"; --0when "0001"=>led<="0110000"; cat<="11111101"; --1when "0010"=>led<="1101101"; cat<="11111011"; --2when "0011"=>led<="1111001"; cat<="11110111"; --3when "0100"=>led<="0110011"; cat<="11101111"; --4when "0101"=>led<="1011011"; cat<="11011111"; --5when others=>led<="0000000"; cat<="11111111";end case;end process;end;//合成数码管显示library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity show isport(cp:in std_logic;rst:in std_logic;lgt:out std_logic_vector(6 downto 0);cat:out std_logic_vector(7 downto 0));end entity;architecture rtl of show iscomponent divport(cp : in std_logic;clk1: out std_logic);end component;signal x:std_logic;component countport(clk,rst: in std_logic;q: out std_logic_vector(3 downto 0));end component;signal y:std_logic_vector(3 downto 0); component yimaqiport(a :in std_logic_vector(3 downto 0);led:out std_logic_vector(6 downto 0);cat:out std_logic_vector(7 downto 0));end component;beginu0:div port map (cp=>cp,clk1=>x);u1:count port map(clk=>x,rst=>rst,q=>y);u2:yimaqi port map(a=>y,cat=>cat,led=>lgt); end rtl;（四）仿真波形1.实验一(2)仿真波形2.实验三(3)仿真波形3.实验四仿真波形（五）仿真波形分析1.实验一(2)仿真波形分析a,b,ci均为输入信号，s,co为输出信号其逻辑功能为：s=a xor b xor cico=( ( a xor b ) and ci ) or (a and b )2.实验三(3)仿真波形分析rst,cp均为输入信号，c,cat为输出信号。