Memory Feature size width (bits) ( m) Chip area (cm^2) Cell area ( m^2) Pitch width ( m)
4k 16k 64k 256k 1M 4M 16M 64M
7 5 3 2 1.3 1 0.5 0.35
0.07 0.1 0.15 0.3 0.2 0.3 0.3 0.6
Time
* The failure rate may increase when a component is used in an 'unfriendly' environment, caused by a stress condition. * An important stress condition is the temperature.
Memory cell array
Read/write logic
Data
* For this model, one is only able to detect a fault.
Chap5. MEMORY TESTING.1
Testing Semies in semiconductor memories have been very impressive. * Their density (bit/chip & bit/area) is ever increasing. * Algorithms with a test time of order O(n^2) are no longer acceptable for testing current mega- and multimega-bit memory chip, where n is the number of bits. * The price of memory chips tends to be stable over longer periods of time. * This makes testing memories an area of concern for practitioners as well as theoreticians who are interested in new test algorithms.
Chap5. MEMORY TESTING.7
Test Time as a Function of Memory Size
* Cycle time: 100 ns
Algorithm complexity Capacity
Testing time (in seconds) 64n 0.1 0.4 1.7 6.7 26.8 1.8 n•log2n 0.023 0.1 0.47 2.1 9.2 40.3 3n3/2 0.63 5.03 40.3 5.4 Mins 43 Mins 5.7 Hrs 2n 2 54 14 Mins 3.8 Hrs 61 Hrs 41 Days 2 Years
Chap5. MEMORY TESTING.10
5
Classification of Failure Mechanisms
* Electrical stress * Intrinsic fa ilure m echanisms
. Electrical overstress . Electrostatic discharge . Gate oxide breakdown . Ionic contamination . Surface charge spreading . Charge effects: Slow trapping, Hot electrons . Piping . Dislocations . Packaging . Metallization . Bounding . Die attachment failures . Particle contamination . Radiation
MTBF = Mean Time Between Failures MTPF = Mean Time between failures due to Permanent Faults ?982 Digital Press, DEC
* Only 2%~13% of the failures are caused by permanent faults.
Chap5. MEMORY TESTING.11
* Extrinsic f ailure mechanisms
Functional DRAM Chip Model
Address Refresh
Address latch Column decoder Refresh logic
Row decoder
Memory cell array
Memory Testing
* Market Share * Test Time * Failure Rate * Functional DRAM Model & Functional Faults * Test Algorithms * DC & AC Parametric Tests * DFT & BIST Aspects * Built-In Testing Schemes * Embedded RAM Tests
n
16k 64k 256k 1M 4M 16M
Mins
Chap5. MEMORY TESTING.8
4
The Importance of Non-Permanent Faults
System CMUA PDP-10 Cm* LSI-11 C.vmp TMR Telettra 1Mx37 RAM Technology ECL NMOS LSI-11 TTL MOS MTBF (hr) MTPF (hr) MTBF/MTPF (ratio) 0.03~0.06 0.03 0.02~0.07 0.06~0.13 0.07 44 800~1600 128 4200 97~328 4900 80~170 1300 106 1450
DRAM Cell Parameters
* The memory cells are placed closely together, which makes them more sensitive to influences of neighboring cell and increases the likelihood of disturbances due to noise on the address and data lines.
100M
# of memory cells per chip # of transistors per chip 64M 16M 4M 1M 80586?
10M 1M 100k
4k 16k 1k 4004 8080 256k
80486 68040 80386 LSI logic 64k 68020 gate array 80286 68000 8086 8085 Microprocessor Memory
Write driver
Sense amplifiers
Data register
Data flow Control flow
Data Data Read/write out in & chip enable
Chap5. MEMORY TESTING.12
6
Functional Faults
* Cell stuck * Read/write line stuck * Data line stuck * Driver stuck * Chip-select line stuck * Open in data line
Chap5. MEMORY TESTING.2
1
Memory Market Share
* DRAM chips are the major part of the memory market.
1988 DRAMs SRAMs ROMs EPROMs EEPROMs* Total 56 17 8 17 2 1990 54 22 8 14 2 1994 58 21 6 12 3
* Cell can be set to 0 but not to 1 (or vice-versa) * Pattern sensitive interaction between cells
Chap5. MEMORY TESTING.13
Reduced Functional Model
Address Address decoder
100% 100% 100%
* Includes flash EEPROMs
?990 Integrated Circuit Engineering Corporation
Chap5. MEMORY TESTING.3
Number of Bits per DRAM: The -Rule
* Historically the number of bits per chip has quadrupled roughly every 3.1 (or ) years.
Chap5. MEMORY TESTING.9
Failure Rate Representation: Bathtub Curve
Burn-in Useful life Wearout
Wearout failures Random failures
Failure rate
Early failures
10k
1k70
74
78
82 Year
86
90
94
?990 Integrated Circuit Engineering Corporation