交通灯实验报告一，实验目的实现两路信号灯交替亮起，并利用两组数码管分别对两路信号进行倒计时。

两路信号时间分别为：V:绿灯（30S）H:红灯（35S）黄灯（5s）绿灯（30S）红灯（35S）黄灯（5S）二，实验步骤建立工程可在欢迎界面点击“Creat a New Project”进入工程建立界面，亦可关闭欢迎界面，点击菜单栏的“File”，点击“New Project Wizard”进入建立工程界面。

右侧为建立工程界面，点击next。

在此界面选定工程路径，取好工程名，点击“Next”。

注意：路径中不能有中文，工程名也不能有中文。

一直点击“Next”进入器件设置界面，DE2-70开发工具采用的Cyclone II系列的EP2C70F896C6N。

点击“Finish”，完成工程建立1、点击“File”，点击“New” 选择“Verilog HDL”2，点击主界面工具栏中的选择“Verilog HDL”3、写入verilog代码。

代码如下：moduletraffic(Clk_50M,Rst,LedR_H,LedG_H,LedY_H,LedR_V,LedG_V,LedY_V,Seg7_VH,Seg7_VL,Seg7_HH,Seg7_HL,led15);parameter S1=2'b00;parameter S2=2'b01;parameter S3=2'b10;parameter S4=2'b11;input Clk_50M,Rst;output LedR_H,LedG_H,LedY_H,LedR_V,LedG_V,LedY_V;output[6:0] Seg7_VH,Seg7_VL,Seg7_HH,Seg7_HL;output led15;//-------------div for 1Hz-------start----reg Clk_1Hz;reg [31:0] Cnt_1Hz;always(posedge Clk_50M or negedge Rst)beginif(!Rst)beginCnt_1Hz<=1;Clk_1Hz<=1;endelsebeginif(Cnt_1Hz>=25000000)beginCnt_1Hz<=1;Clk_1Hz<=~Clk_1Hz;endelseCnt_1Hz<=Cnt_1Hz + 1;endend//-----------div for 1Hz------end-----reg[7:0] Cnt30,CntH,CntV,CntHH,CntVV;reg[7:0] CntDis,CntDiss;//-----------30 counter and seg7---start---reg LedR_H,LedG_H,LedY_H,LedR_V,LedG_V,LedY_V;always(posedge Clk_1Hz)begincase(state)S1:beginif(Cnt30>=30)Cnt30<=1;elseCnt30<=Cnt30 + 1;endS2:beginif(Cnt30>=5)Cnt30<=1;elseCnt30<=Cnt30 + 1;endS3:beginif(Cnt30>=30)Cnt30<=1;elseCnt30<=Cnt30 + 1;endS4:beginif(Cnt30>=5)Cnt30<=1;elseCnt30<=Cnt30 + 1;endendcaseendalways(posedge Clk_1Hz) begincase(stateV)S1:beginif(CntV>=30)CntV<=1;elseCntV<=CntV + 1;endS2:beginif(CntV>=5)CntV<=1;elseCntV<=CntV + 1;endS3:beginif(CntV>=35)CntV<=1;elseCntV<=CntV + 1;endendcaseendalways(posedge Clk_1Hz)begincase(stateH)S1:beginif(CntH>=35)CntH<=1;elseCntH<=CntH + 1;endS2:beginif(CntH>=30)CntH<=1;elseCntH<=CntH + 1;endS3:beginif(CntH>=5)CntH<=1;elseCntH<=CntH + 1;endendcaseendalways(negedge Clk_50M or negedge Rst) begincase(state)S1:CntVV=30-CntV;S2:CntVV=5-CntV;S3:CntVV=35-CntV;S4:CntVV=35-CntV;endcaseendalways(negedge Clk_50M or negedge Rst)begincase(state)S1:CntHH=35-CntH;S2:CntHH=35-CntH;S3:CntHH=30-CntH;S4:CntHH=5-CntH;endcaseend//16进制计数器转换为用于显示的10进制计数器always(posedge Clk_50M)beginif(CntVV>29)beginCntDis[7:4]<=3;CntDis[3:0]<=CntVV - 30;endelse if(CntVV>19)beginCntDis[7:4]<=2;CntDis[3:0]<=CntVV - 20;endelse if(CntVV>9)beginCntDis[7:4]<=1;CntDis[3:0]<=CntVV - 10;elseCntDis<=CntVV;endSEG7_LUT hex4(Seg7_VL,CntDis[3:0]); SEG7_LUT hex5(Seg7_VH,CntDis[7:4]);always(posedge Clk_50M)beginif(CntHH>29)beginCntDiss[7:4]<=3;CntDiss[3:0]<=CntHH - 30;endelse if(CntHH>19)beginCntDiss[7:4]<=2;CntDiss[3:0]<=CntHH - 20;endelse if(CntHH>9)beginCntDiss[7:4]<=1;CntDiss[3:0]<=CntHH - 10;endelseCntDiss<=CntHH;endSEG7_LUT hex1(Seg7_HL,CntDiss[3:0]); SEG7_LUT hex2(Seg7_HH,CntDiss[7:4]); //-----------30 counter and seg7----end---- reg [1:0]state,stateH,stateV;always(posedge Clk_1Hz)begincase(state)S1:if(Cnt30>=30)beginstate<=S2;endS2:if(Cnt30>=5)beginstate<=S3;S3:if(Cnt30>=30)beginstate<=S4;endS4:if(Cnt30>=5)beginstate<=S1;enddefault:beginstate<=S1;endendcaseendalways(posedge Clk_1Hz)begincase(state)S1:beginstateH<=S1;stateV<=S1;endS2:beginstateH<=S1;stateV<=S2;endS3:beginstateH<=S2;stateV<=S3;endS4:beginstateH<=S3;stateV<=S3;endendcaseendalways(posedge Clk_50M or negedge Rst)beginif(!Rst)beginLedR_H<=0;LedG_H<=0;LedY_H<=0;LedR_V<=0;LedG_V<=0;LedY_V<=0;endelsebegincase(state)S1:beginLedR_H<=1;LedG_H<=0;LedY_H<=0;LedR_V<=0;LedG_V<=1;LedY_V<=0;endS2:beginLedR_H<=1;LedG_H<=0;LedY_H<=0;LedR_V<=0;LedG_V<=0;LedY_V<=1;endS3:beginLedR_H<=0;LedG_H<=1;LedY_H<=0;LedR_V<=1;LedG_V<=0;LedY_V<=0;endS4:beginLedR_H<=0;LedG_H<=0;LedY_H<=1;LedR_V<=1;LedG_V<=0;LedY_V<=0;enddefault:beginLedR_H<=0;LedG_H<=0;LedY_H<=0;LedR_V<=0;LedG_V<=0;LedY_V<=0;endendcaseendendassign led15=state;endmodulemodule SEG7_LUT ( oSEG,iDIG );input [3:0] iDIG;output [6:0] oSEG;reg [6:0] oSEG;always (iDIG)begincase(iDIG)4'h1: oSEG = 7'b1111001; // ---t----4'h2: oSEG = 7'b0100100; // | |4'h3: oSEG = 7'b0110000; // lt rt4'h4: oSEG = 7'b0011001; // | |4'h5: oSEG = 7'b0010010; // ---m----4'h6: oSEG = 7'b0000010; // | |4'h7: oSEG = 7'b1111000; // lb rb4'h8: oSEG = 7'b0000000; // | |4'h9: oSEG = 7'b0011000; // ---b----4'ha: oSEG = 7'b0001000;4'hb: oSEG = 7'b0000011;4'hc: oSEG = 7'b1000110;4'hd: oSEG = 7'b0100001;4'he: oSEG = 7'b0000110;4'hf: oSEG = 7'b0001110;4'h0: oSEG = 7'b1000000;endcaseendendmodule编译工程保存文件，将文件放在所建工程所在路径下点击主界面工具栏中的图标也可点击菜单栏中“Processing”，点击“Start Compilation”分配关键如下：Clk_50M Input PIN_AD15LedG_H Output PIN_AD9LedG_V Output PIN_AJ6LedR_H Output PIN_AJ7 )LedR_V Output PIN_AJ5 )LedY_H Output PIN_AD8LedY_V Output PIN_AK5Rst Input PIN_AA23Seg7_HH[6] Output PIN_G1Seg7_HH[5] Output PIN_H3Seg7_HH[4] Output PIN_H2Seg7_HH[3] Output PIN_H1Seg7_HH[2] Output PIN_J2Seg7_HH[1] Output PIN_J1Seg7_HH[0] Output PIN_K3Seg7_HL[6] Output PIN_E4Seg7_HL[5] Output PIN_F4Seg7_HL[4] Output PIN_G4Seg7_HL[3] Output PIN_H8Seg7_HL[2] Output PIN_H7Seg7_HL[1] Output PIN_H4Seg7_HL[0] Output PIN_H6Seg7_VH[6] Output PIN_AD17Seg7_VH[5] Output PIN_AF17 7Seg7_VH[4] Output PIN_AE17 7Seg7_VH[3] Output PIN_AG16Seg7_VH[2] Output PIN_AF16 7Seg7_VH[1] Output PIN_AE16 7Seg7_VH[0] Output PIN_AG13Seg7_VL[6] Output PIN_AD12Seg7_VL[5] Output PIN_AD11Seg7_VL[4] Output PIN_AF10 8Seg7_VL[3] Output PIN_AD10Seg7_VL[2] Output PIN_AH9 8Seg7_VL[1] Output PIN_AF9 8Seg7_VL[0] Output PIN_AE8 8烧写代码在管脚配置完成后，还需将工程再编译一次，成功后，点击主界面工具栏中的亦可点击主界面菜单栏中“Tools”，点击“Programmer”进入代码烧写界面后，点击“Start”，当“Progress”为100%时，表示烧写完成，这是可观察DE2-70板现象获得预期的效果，两组的信号红黄绿灯交替切换，计数器记为零时信号灯切换状态，红灯35s，黄灯5s，绿灯30s。