CZ3001 Advanced Computer Architecture: Instruction Level Parallelism
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Pipeline Hazards
Pipeline Hazards
Pipelining works well when pipelines are continuously operating and full. Efficiency drops if the units in the pipeline are free (as can be seen from the efficiency equation). Stalling of the pipeline causes efficiency to drop. Any condition that causes the pipeline to stall is called a hazard.
Various types of hazards are data hazard, control/instruction hazard and structural hazard. Hardware interlock is needed to install the pipeline stall when hazard happens.
ADD R8, R2, R2 ADD R7, R3, R4
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Data Hazards
Data hazards There are three types of data dependencies: RAW (read-after-write) dependency (true dependency), WAW (write-after-write) dependency (output dependency) and WAR (write-after-read) dependency (antidependency). These dependencies are explicit and can be detected and pipeline stall can be handled. The detection and handling of hazards can be done in software (in compiler etc.) or in hardware. Data dependent hazards depend on both the structure of the instruction pipeline and the order of the instructions.
SUB R3, R2, R1 AND R9, R7, R3
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Pipeline Hazards
Time (clock cycles)
ALU
I SUB R3, R2, R1 n s t AND R9, R7, R3 r.
IM Reg p1
Loop1: ADD
Address calculation
Data hazard: A data hazard is any condition in which either the source or destination operands of an instruction are not available at the time expected in the pipeline. As a result some operation has to be delayed, and the pipeline stalls.
IM Reg
R1, R2, R3
ALU
DM Reg Reg
Update PC
DM Reg IM Reg
ALU
ALU
DM Reg DM Reg
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Pipeline Hazards
Control/Instruction hazard: The pipeline may be stalled because of a delay in the availability of an instruction. In the event of a miss in the cache, the instruction has to be fetched from main memory which introduces delay in the instruction fetch and the pipeline stalls. Conditional and unconditional jumps, subroutine calls, and other program control instructions can cause the pipeline to stall. These stalls also belong to control/instruction hazard.
J
loop1
Loop1: ADD R1, R2, R3
Structural hazard: Some time, two instructions require the use of a given hardware resource at the same time and this leads to a stall in the pipeline. One of the example is: write stage access the memory/cache for writing the result and the instruction fetch stage tries to fetch the instruction from the memory/cache at the same time. In general structural hazards are avoided by providing sufficient hardware resources on the processor chip.