Master config
Slave config
3
TIM2
General purpose
32 bit
1...65536
YES
4
YES
YES
TIM3 and TIM4
Basic
16 bit
1…65536
YES
4
YES
YES
TIM6 and TIM7
1 channel, 1 complementary output
TIM2/5
TIM3/4/19
TIM12
TIM15
TIM13/14
TIM16/17
TIM6/7/18
Features overview (1/3)
ETR
5
• Up to 4 16-bit resolution Capture Compare channels (TIM3/4/19) • Up to 4 32-bit resolution Capture Compare channels (TIM2/5) • Inter-timers synchronization
TIM3/4/19
Counting Modes (2/2)
• There is only one counting mode:
• Up counting mode
9
Up counting
Update Event
TIM12
TIM15
TIM13/14
TIM16/17
TIM6/7/18
Update Event
Trigger Output
16-Bit Prescaler Auto Reload REG +/- 16/32-Bit Counter
CH1
CH1
CH1 Comp
Capture Compare
TIM2/5
TIM3/4/19
TIM12
TIM15
TIM13/14
TIM16/17
TIM6/7/18
Counting Modes (1/2)
TIM2/5
TIM3/4/19
TIM12
TIM15
TIM13/14
TIM16/17
TIM6/7/18
STM32F37x Timer features overview
Counter resolution
General purpose
4
Counter Type
Up, Down and Up/Down Up, Down and Up/Down
• • • • Prescaler off Division by 2 Division by 4 Division by 8
ITR1
ITR2 ITR3 ITR4 TI1F_ED TI1FP1 TI2FP2
Controller
TRGO
TIM2/5
TIM3/4/19
TIM12
TIM15
Capture Compare Array presentation
STM32F3 Technical Training
For reference only
Refer to the latest documents for details
General Purpose Timers
(TIM2/3/4/5 - TIM12/13/14 - TIM15/16/17 - TIM6/7/18)
Prescaler factor
DMA
Capture Compare channels
Synchronization
Master config
Slave config
TIM2 and TIM5
General purpose
32 bit
1...65536
1…65536
YES
4
YES
YES
TIM3, TIM4 and TIM19
ETR
Clock ITR 1
6
Trigger/Clock Controller
Trigger Output
• Up to 2 16-bit resolution Capture Compare channels
• Inter-timers synchronization • Encoder Interface • Only TIM15 has complementery output on channel1
Polarity selection & Edge Detector & Prescaler & Filter
Trigger Controller
ETR
• External pin ETR
• • • • Enable/Disable bit Programable polarity 4 Bits External Trigger Filter External Trigger Prescaler:
• ITR1 / ITR2 / ITR3 / ITR4 • Using one timer as prescaler for another timer
TIMxCLK
11
• External Capture Compare pins
• Pin 1: TI1FP1 or TI1F_ED • Pin 2: TI2FP2
• Input direction: channel configured in Capture mode • Output direction: Channel configured in Compare mode • Channel’s main functional blocs
• Capture/Compare register • Input stage for capture
• Next to counter overflow/underflow event • Nest to Counter overflow/underflow event plus the following events
• Setting the UG bit by software • Trigger active edge detection (through the slave mode controller)
Basic
16 bit
YES
4
YES
YES
TIM6, TIM7 and TIM18
1 channel, 1 complementary output
16 bit
Up
1…65536
YES
0
YES
NO
16 bit
Up
1…65536
NO
1
YES(1)
NO
TIM16 and TIM17
2 channels, 1 complementary output
TIM2/5
TIM3/4/19
TIM12
TIM15
TIM13/14
TIM16/17
Counter Clock Selection
• Clock can be selected out of 8 sources
• Internal clock TIMxCLK provided by the RCC • Internal trigger input 1 to 4:
• Capture stage architecture
13
TI1
Input Filter & Edge detector
TRC
IC1
Prescaler
16 bit Capture/Compare 1 Register
• The Update Event is generated
• For each counter overflow/underflow • Through software, by setting the UG bit (Update Generation)
• The Update Event (UEV) request source can be configured to be
• • 4-bit digital filter Input Capture Prescaler:
• Output stage for Compare
• Output control bloc
TIM2/5
TIM3/4/19
TIM12
TIM15
TIM13/14
TIM16/17
Input Capture Mode (1/2)
• There are three counter modes:
• Up counting mode • Down counting mode • Center-aligned mode
8
Center Aligned
Up counting
Down counting
Update Event
TIM2/5
Clock ITR 1 ITR 2 ITR 3 ITR 4
Trigger/Clock Controller
Trigger Output
16-Bit Prescaler Auto Reload REG +/- 16/32-Bit Counter
• Up to 6 IT/DMA Requests
CH1
CH1
16 bit
36
NO
2
YES
YES
TIM15
1 channel
TIM13 and TIM14
2 channels
16 bit 16 bit