1.三与门library ieee;use ieee.std_logic_1164.all;entity yumen isport(a,b,c : in std_logic;f : out std_logic);end yumen;architecture and3_1 of yumen isbeginf<=a and b and c;end architecture and3_1;2.三八译码器library ieee;use ieee.std_logic_1164.all;entity jg isport(a,b,c,g1,g2a,g2b:in std_logic;y:out std_logic_vector(7 downto 0));end entity jg;architecture rt1 of jg issignal indata:std_logic_vector(2 downto 0); beginindata<=c&b&a;process(indata,g1,g2a,g2b)isbeginif(g1='1' and g2a='0' and g2b='0')then case indata iswhen"000"=>y<="11111110"; when"001"=>y<="11111101"; when"010"=>y<="11111011"; when"011"=>y<="11110111"; when"100"=>y<="11101111"; when"101"=>y<="11011111"; when"110"=>y<="10111111"; when"111"=>y<="01111111";when others=>y<="xxxxxxxx";end case;elsey<="11111111";end if;end process;end rt1; 3.同步复位/置位、下降沿触发的d触发器ibrary ieee;use ieee.std_logic_1164.all;entity adff isport(clk,d,r,s:in std_logic;q:out std_logic);end adff;architecture rtl of adff issignal q_temp,qb_temp:std_logic;beginprocess(clk,r,s)beginif(clk'event and clk='0')thenif(r='0' and s='1')thenq_temp<='1';if(r='1' and s='0')thenq_temp<='0';elseq_temp<=d;end if;end if;end if;end process;q<=q_temp;end rtl;4.异步复位/置位、上升沿触发的d发器ibrary ieee;use ieee.std_logic_1164.all;entity adff isport(clk,d,r,s:in std_logic;q:out std_logic);end adff;architecture rtl of adff issignal q_temp,qb_temp:std_logic;beginprocess(clk,r,s)beginif(r='0' and s='1')thenq_temp<='1';elsif(r='1' and s='0')thenq_temp<='0';elsif(clk'event and clk='1')thenq_temp<=d;end if;end process;q<=q_temp;end rtl;5.四分频器ibrary ieee;use ieee.std_logic_1164.all;entity one isport( clk1:in std_logic;clk4:out std_logic);end one;architecture one1 of one issignal data1:integer range 0 to 10;signal q1:std_logic;beginprocess(clk1)beginif rising_edge(clk1) thenif(data1=1) thendata1<=0;q1<=not q1;elsedata1<=data1+1;end if;end if;clk4<=q1;end process;end architecture one1;6.四选一library ieee;use ieee.std_logic_1164.all;entity mux4 isport(input:in std_logic_vector(3 downto 0); a,b:in std_logic;y : out std_logic);end mux4 ;architecture rtl of mux4 issignal sel:std_logic_vector(1 downto 0); beginsel<=b & a;process (input,sel)beginif (sel="00") theny <= input(0);elsif (sel="01") theny <= input(1);elsif (sel="10") theny <= input(2);elsey <= input(3);end if;end process;end rtl; 7.五分频器use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fenpin5 isport (rst,clkin :in std_logic;clkout:out std_logic);end fenpin5;architecture rtl of fenpin5 issignal count1,count2: std_logic_vector(7 downto 0);signal tmp,tmp1,tmp2: std_logic;begintmp<=tmp1 and tmp2;clkout<=tmp xor tmp1;process(clkin,rst)beginif rst ='1'thencount1 <= "00000000";tmp1<= '0';elsif clkin'event and clkin='1' thenif count1 = "00000100" thencount1 <= "00000000";elsecount1 <= count1 + 1;if count1 < "00000010" thentmp1<= '0';elsetmp1<= '1';end if;end if;end if;end process;end rtl;8.moore状态机library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity moore isport (rst,clk,x:in std_logic; op:out std_logic);end moore;architecture a of moore is type state is (s0,s1,s2,s3); signal st: state;beginstate_comp: process(rst,clk) beginif rst='1' thenst <= s0;elsif rising_edge(clk) then case st iswhen s0 =>if x = '0' thenst <= s0;elsest <= s1;end if;op <= '1';when s1 =>if x = '0' thenst <= s3;elsest <= s2;end if;op <= '1';when s2=>if x = '0' thenst <= s2;elsest <= s3;end if;op <= '1';when s3=>if x = '0' thenst <= s3;elsest <= s0;end if;op <= '0';end case;end if; 9.mealy状态机library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mealy isport (rst,clk,x:in std_logic; op:out std_logic);end mealy;architecture a of mealy istype state is (s0,s1,s2,s3); signal st : state;beginstate_comp: process(rst,clk) beginif rst='1' thenst <= s0;elsif rising_edge(clk) then case st iswhen s0 =>if x = '0' thenst <= s0; op <= '0';elsest <= s1; op <= '1';end if;when s1 =>if x = '0' thenst <= s3; op <= '1';elsest <= s2; op <= '1';end if;when s2 =>if x = '0' thenst <= s2; op <= '0';elsest <= s3; op <= '1';end if;when s3 =>if x = '0' thenst <= s3; op <= '0';elsest <= s0; op <= '0';end if;end case;end if;end process state_comp;end a10.全加器library ieee;use ieee.std_logic_1164.all;entity full_adder isport (a,b,cin:in std_logic;s,co:out std_logic);end full_adder;architecture full1 of full_adder issignal tmp1,tmp2,tmp3:std_logic;begintmp1 <= a xor b;tmp2 <= a and b;tmp3 <= tmp1 and cin;s <= tmp1 xor cin;co <= tmp2 or tmp3;end full1;11.同步12进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count12en isport (clk,clr, en :in std_logic;qa,qb,qc,qd:out std_logic);end count12en;architecture rtl of count12en issignal count_4:std_logic_vector(3 downto 0); beginqa<=count_4(0);qb<=count_4(1);qc<=count_4(2);qd<=count_4(3);process (clr,clk)beginif(clr='1') thencount_4<="0000";elsif (clk'event and clk ='1') thenif(en='1') thenif (count_4="1011") thencount_4<="0000";elsecount_4<=count_4+'1';end if;end if;end if;end process;end rtl; 12.优先编码器library ieee;use ieee.std_logic_1164.all;entity priority_encoder isport(input:in std_logic_vector(7 downto 0); y : out std_logic_vector(2 downto 0));end priority_encoder;architecture rtl of priority_encoder is beginp1: process (input)beginif ( input(0) ='0') theny <= "111";elsif (input(1) ='0') theny <= "110";elsif (input(2) ='0') theny <= "101";elsif (input(3) ='0') theny <= "100";elsif (input(4) ='0') theny <= "011";elsif (input(5) ='0') theny <= "010";elsif (input(6) ='0') theny <= "001";elsey <= "000";end if;end process p1;end rtl;。