哈尔滨理工大学软件学院课程设计报告课程片上计算机系统题目 CPU模型机设计班级集成12-1班专业集成电路设计与集成系统学生张铭学号 1214020130指导教师崔林海2014年07 月02日索引：1．课程设计的目的及要求 (3)2．处理器的设计思想和设计内容 (3)3．设计处理器的结构和实现方法 (3)4．模型机的指令系统 (4)5．处理器的状态跳转操作过程 (4)6. CPU的VHDL代码 (7)7. 模型机在Quartus II环境下的应用 (32)8. 仿真波形 (33)9. 课程设计的总结 (35)一．课程设计的目的及要求：1.目的：了解Quartus II软件的应用，学习Quartus II环境下设计CPU的基本过程；掌握CPU设计代码的含义以及CPU的工作原理；了解CPU与内存RAM 间的连接数据的传输过程；学习在Quartus II环境下建立模型机的具体过程。

融会贯通本课程各章节的内容，通过知识的综合运用，加深对计算机系统各模块的工作原理及相互联系的认识。

学习设计和调试计算机的基本步骤和方法，提高使用软件仿真工具和集成电路的基本技能。

培养科学研究的独立工作能力，取得工程设计与组装调试的实践和经验。

2.要求：以《计算机组成与设计》书中123页的简化模型为基础，更改其指令系统，形成设计者的CPU，在Quartus II环境下与主存连接，调试程序，观察指令的执行是否达到设计构想。

二．处理器的设计思想和设计内容：处理器的字长为16b；包括四种指令格式，格式1、格式2、格式3的指令字长度为8b，格式4的指令字长度为16b；处理器内部的状态机包括6个状态。

关于CPU：操作码5位，一共设计20条指令，主要包括空操作指令、中断指令、加法指令、减法指令、三种逻辑运算指令、循环移位操作指令，数据传输指令，转移类指令，特权指令，取反，取绝对值等等。

关于RAM：地址线设置成16bits，主存空间为64words。

书中原CPU的主要修改：（1）模型机CPU指令集中的逻辑左移与逻辑右移改成逻辑循环右移与逻辑循环左移。

（2）模型机CPU指令集中的or改成not。

（3）模型机CPU指令的执行流程及状态跳转。

三．设计处理器的结构和实现方法：（指令格式）格式1：寄存器寻址方式15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0内存（2的12次方）四．模型机的指令系统五．处理器的状态跳转操作过程：(二)、简单指令执行状态描述读内存指令：（1）St_0：取指令执行以下操作；1）M_address←(MAR) 把指令地址送到地址总线2）令Write-Read←’0’向内存发出读命令（取指令）3）IR(15..0)←M_data_in（15..0）将读出的指令加载于IR(15..0)4）PC=PC+1 至此指令已经全部取出，存在于IR(15..0)，为取下一条指令准备地址（2）St_1：NULL 直接跳转到下一状态（3）St_2：MAR←IR(11..0)将数据地址加载于MAR（4）St_3：1）M_address←(MAR)把数据地址送到地址总线2）令Write-Read←’0’向内存发出读命令（取数据）3）MAR←PC 把下一条指令地址加载于MAR（5）St_4：1）R0←M_data_in 将来自内存的数据加载于R0，本指令执行完毕2）M_address←(MAR) 把下一条指令地址送到地址总线3）令Write-Read←’0’向内存发出读命令（取下一条指令）4）下一状态跳转到St_0无条件转移指令（1）St_0：取指令执行以下操作；1）M_address←(MAR) 把指令地址送到地址总线2）令Write-Read←’0’向内存发出读命令（取指令）3）IR(15..0)←M_data_in（15..0）将读出的指令加载于IR(15..0)4）PC=PC+1 （此语句无用，因为程序计数器后续重新复制达到无条件转移目的）（2）St_1：NULL 直接跳转到下一状态（3）St_2：1）MAR←IR(11..0) 将转移目标地址加载于MAR2）PC←IR(11..0) 将转移目标地址加载于PC（4）St_3：1) M_address←(MAR) 把下一条指令地址送到地址总线2)令Write-Read←’0’向内存发出读命令（取下一条指令）3)下一状态跳转到St_0六．CPU的VHDL代码：LIBRARY ieee;USE ieee.std_logic_1164.ALL;PACKAGE namespack ISCONSTANT idle : std_logic_vector(4 DOWNTO 0) :="00000";CONSTANT load : std_logic_vector(4 DOWNTO 0) :="00001";CONSTANT move : std_logic_vector(4 DOWNTO 0) :="00010";CONSTANT addP : std_logic_vector(4 DOWNTO 0) :="00011";CONSTANT subp : std_logic_vector(4 DOWNTO 0) :="00100";CONSTANT andp : std_logic_vector(4 DOWNTO 0) :="00101";CONSTANT orp : std_logic_vector(4 DOWNTO 0) :="00110";CONSTANT xorp : std_logic_vector(4 DOWNTO 0) :="00111";CONSTANT shrp : std_logic_vector(4 DOWNTO 0) :="01000";CONSTANT shlp : std_logic_vector(4 DOWNTO 0) :="01001";CONSTANT swap : std_logic_vector(4 DOWNTO 0) :="01010";CONSTANT jmp : std_logic_vector(4 DOWNTO 0) :="01011";CONSTANT jz : std_logic_vector(4 DOWNTO 0) :="01100";CONSTANT read : std_logic_vector(4 DOWNTO 0) :="01101";CONSTANT write : std_logic_vector(4 DOWNTO 0) :="01110";CONSTANT stop : std_logic_vector(4 DOWNTO 0) :="01111";CONSTANT comp : std_logic_vector(4 DOWNTO 0) :="10000";CONSTANT notp : std_logic_vector(4 DOWNTO 0) :="10001";CONSTANT clear : std_logic_vector(4 DOWNTO 0) :="10010";CONSTANT absp : std_logic_vector(4 DOWNTO 0) :="10011";CONSTANT modp : std_logic_vector(4 DOWNTO 0) :="10100";END namespack;LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;USE spack.ALL;ENTITY cpu ISPORT(reset : IN std_logic; --清零信号低有效clock : IN std_logic; --时钟信号Write_Read: OUT std_logic; --读写信号,'1'为写M_address: OUT std_logic_vector(10 DOWNTO 0); --地址线M_data_in: IN std_logic_vector(7 DOWNTO 0); --数据输入线M_data_out: OUT std_logic_vector(7 DOWNTO 0); --数据输出线overflow: OUT std_logic --溢出标志);END cpu;ARCHITECTURE RTL OF cpu ISSIGNAL IR: std_logic_vector(15 DOWNTO 0); --指令寄存器SIGNAL MDR: std_logic_vector(7 DOWNTO 0); --数据寄存器SIGNAL MAR: std_logic_vector(10 DOWNTO 0); --地址寄存器SIGNAL status: integer RANGE 0 TO 6; --状态寄存器BEGINstatus_change: PROCESS(reset, clock, status )BEGINIF reset = '0' THEN status <= 0 ; -- 进入初始状态ELSIF clock'EVENT AND clock = '0' THENCASE status ISWHEN 0 =>status <= 1;WHEN 1 =>IF IR(15 DOWNTO 11)= Stop THENstatus <= 1;ELSEstatus <= 2;END IF;WHEN 2 =>CASE IR(15 DOWNTO 11) ISWHEN Swap|Jmp|Jz|Read|Write =>status <= 3;WHEN OTHERS =>status <= 0;END CASE;WHEN 3 =>IF IR(15 DOWNTO 11)= Swap THENstatus <= 0;ELSEstatus <= 4;END IF;WHEN 4 =>status <= 5;WHEN 5 =>CASE IR(15 DOWNTO 11) ISWHEN Read|Write =>status <= 6;WHEN OTHERS =>status <= 0;END CASE;WHEN 6=>CASE IR(15 DOWNTO 11) ISWHEN Comp=>status<=0;WHEN NotP=>status<=0;WHEN Clear=>status<=0;WHEN AbsP=>status<=0;WHEN ModP=>status<=0;WHEN OTHERS=>status <= 0;END CASE;END CASE;END IF;END PROCESS status_change;seq: PROCESS(reset,clock)V ARIABLE PC:std_logic_vector(10 DOWNTO 0);--程序计数器V ARIABLE R0,R1,R2,R3: std_logic_vector(7 DOWNTO 0); --通用寄存器V ARIABLE A: std_logic_vector(7 DOWNTO 0); --临时寄存器V ARIABLE RC: std_logic_vector(7 DOWNTO 0); --比较结果寄存器V ARIABLE RM: std_logic_vector(7 DOWNTO 0); --取模结果寄存器V ARIABLE temp: std_logic_vector(8 DOWNTO 0);--临时变量BEGINIF(reset='0') THEN -- 进入初始状态IR <= (OTHERS=>'0');PC := (OTHERS=>'0');R0 := (OTHERS=>'0');R1 := (OTHERS=>'0');R2 := (OTHERS=>'0');R3 := (OTHERS=>'0');A := (OTHERS=>'0');MAR <= (OTHERS=>'0');MDR <= (OTHERS=>'0');ELSIF(clock'event AND clock='1') THENoverflow <= '0';CASE status ISWHEN 0=> --状态0IR <= M_data_in & "00000000"; --取指令PC := PC+1; --程序计数器加1WHEN 1=> --状态1IF (IR(15 DOWNTO 11) /= Stop) THENMAR <= PC;END IF;CASE IR(15 DOWNTO 11) ISWHEN Load =>R0:="0000" & IR(10 DOWNTO 7);WHEN Move => --Move Rx,Ry;CASE IR(10 DOWNTO 7) ISWHEN "0001"=> R0:=R1;WHEN "0010"=> R0:=R2;WHEN "0011"=> R0:=R3;WHEN "0100"=> R1:=R0;WHEN "0110"=> R1:=R2;WHEN "0111"=> R1:=R3;WHEN "1000"=> R2:=R0;WHEN "1001"=> R2:=R1;WHEN "1011"=> R2:=R3;WHEN "1100"=> R3:=R0;WHEN "1101"=> R3:=R1;WHEN "1110"=> R3:=R2;WHEN OTHERS=> NULL;END CASE;WHEN Shrp => --逻辑右移1位；CASE IR(10 DOWNTO 9) ISWHEN "00"=>R0:='0'&R0(7 DOWNTO 1);WHEN "01"=>R1:='0'&R1(7 DOWNTO 1);WHEN "10"=>R2:='0'&R2(7 DOWNTO 1);WHEN OTHERS=>R3:='0'&R3(7 DOWNTO 1);END CASE;WHEN Shlp => --逻辑左移1位；CASE IR(10 DOWNTO 9) ISWHEN "00"=>R0:=R0(6 DOWNTO 0)&'0';WHEN "01"=>R1:=R1(6 DOWNTO 0)&'0';WHEN "10"=>R2:=R2(6 DOWNTO 0)&'0';WHEN OTHERS=>R3:=R3(6 DOWNTO 0)&'0';END CASE;WHEN Addp|Subp|Andp|Orp|Xorp|Swap =>CASE IR(8 DOWNTO 7) ISWHEN "00"=> A:=R0;WHEN "01"=> A:=R1;WHEN "10"=> A:=R2;WHEN OTHERS=> A:=R3;END CASE;WHEN OTHERS => NULL;END CASE;WHEN 2=> --状态2CASE IR(15 DOWNTO 11) ISWHEN Addp => --Rx:= Rx+A;CASE IR(10 DOWNTO 9) ISWHEN "00"=>temp := (R0(7) & R0(7 DOWNTO 0)) + (A(7) & A(7 DOWNTO 0));R0:=temp(7 DOWNTO 0);overflow <= temp(8) XOR temp(7);WHEN "01"=>temp :=(R1(7) & R1(7 DOWNTO 0)) + (A(7) & A(7 DOWNTO 0));R1:=temp(7 DOWNTO 0);overflow <= temp(8) XOR temp(7);WHEN "10"=>temp :=(R2(7) & R2(7 DOWNTO 0)) + (A(7) & A(7 DOWNTO 0));R2:=temp(7 DOWNTO 0);overflow <= temp(8) XOR temp(7);WHEN OTHERS=>temp :=(R3(7) & R3(7 DOWNTO 0)) + (A(7) & A(7 DOWNTO 0));R3:=temp(7 DOWNTO 0);overflow <= temp(8) XOR temp(7);END CASE;WHEN Subp => --Rx:= Rx-A;CASE IR(10 DOWNTO 9) ISWHEN "00"=>temp :=(R0(7) & R0(7 DOWNTO 0)) + NOT(A(7) & A(7 DOWNTO 0)) + 1;R0:=temp(7 DOWNTO 0);overflow <= temp(8) XOR temp(7);WHEN "01"=>temp :=(R1(7) & R1(7 DOWNTO 0)) + NOT(A(7) & A(7 DOWNTO 0)) + 1;R1:=temp(7 DOWNTO 0);overflow <= temp(8) XOR temp(7);WHEN "10"=>temp :=(R2(7) & R2(7 DOWNTO 0)) + NOT(A(7) & A(7 DOWNTO 0)) + 1;R2:=temp(7 DOWNTO 0);overflow <= temp(8) XOR temp(7);WHEN OTHERS=>temp :=(R3(7) & R3(7 DOWNTO 0)) + NOT(A(7) & A(7 DOWNTO 0)) + 1;R3:=temp(7 DOWNTO 0);overflow <= temp(8) XOR temp(7);END CASE;WHEN Andp => -- Rx:= Rx AND A;CASE IR(10 DOWNTO 9) ISWHEN "00"=>R0:=R0 and A;WHEN "01"=>R1:=R1 and A;WHEN "10"=>R2:=R2 and A;WHEN OTHERS=>R3:=R3 and A;END CASE;WHEN Orp => -- Rx := Rx OR A;CASE IR(10 DOWNTO 9) ISWHEN "00"=>R0:=R0 or A;WHEN "01"=>R1:=R1 or A;WHEN "10"=>R2:=R2 or A;WHEN OTHERS=>R3:=R3 or A;END CASE;WHEN Xorp => --Rx=Rx XOR A;CASE IR(10 DOWNTO 9) ISWHEN "00"=>R0:=R0 XOR A;WHEN "01"=>R1:=R1 XOR A;WHEN "10"=>R2:=R2 XOR A;WHEN OTHERS=>R3:=R3 XOR A;END CASE;WHEN Swap => --Swap: Rx to Ry;CASE IR(10 DOWNTO 7) ISWHEN "0100"=>R0:=R1;WHEN "1000"=>R0:=R2;WHEN "1100"=>R0:=R3;WHEN "0001"=>R1:=R0;WHEN "1001"=>R1:=R2;WHEN "1101"=>R1:=R3;WHEN "0010"=>R2:=R0;WHEN "0110"=>R2:=R1;WHEN "1110"=>R2:=R3;WHEN "0111"=>R3:=R1;WHEN "1011"=>R3:=R2;WHEN "0011"=>R3:=R0;WHEN OTHERS=>NULL;END CASE;WHEN OTHERS => NULL;END CASE;WHEN 3=> --状态3CASE IR(15 DOWNTO 11) ISWHEN "01010"=> --SwapCASE IR(10 DOWNTO 9) ISWHEN "00"=> R0:=A;WHEN "01"=> R1:=A;WHEN "10"=> R2:=A;WHEN OTHERS=> R3:=A;END CASE;WHEN Jmp|Jz|Read|Write =>IR(7 DOWNTO 0)<= M_data_in; -- 取双字节指令的后半部PC := PC+1;WHEN OTHERS => NULL;END CASE;WHEN 4=> --状态4CASE IR(15 DOWNTO 11) ISWHEN Jmp =>PC := IR(10 DOWNTO 0);MAR <= IR(10 DOWNTO 0);WHEN Jz =>IF(R0="00000000") THENPC := IR(10 DOWNTO 0);MAR <= IR(10 DOWNTO 0);ELSEMAR <= PC;END IF;WHEN Read =>MAR <= IR(10 DOWNTO 0);WHEN Write =>MAR <= IR(10 DOWNTO 0);MDR <= R0;WHEN OTHERS => NULL;END CASE;WHEN 5=> --状态5MAR <= PC;WHEN 6=> --状态6CASE IR(15 DOWNTO 11) ISWHEN Comp => --比较CASE IR(10 DOWNTO 7) ISWHEN "0001"=> A:=R1-R0;IF A(7 DOWNTO 0)="00000000" THENRC(7 DOWNTO 6):="00"; --相等ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01"; --R0>R1ELSE RC(7 DOWNTO 6):="10"; --R0<R1END IF;WHEN "0010"=> A:=R2-R0;IF A(7 DOWNTO 0)="00000000" THENRC(7 DOWNTO 6):="00";ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01";ELSE RC(7 DOWNTO 6):="10" ;END IF;WHEN "0011"=> A:=R3-R0;IF A(7 DOWNTO 0)="00000000" THENRC(7 DOWNTO 6):="00";ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01";ELSE RC(7 DOWNTO 6):="10";END IF;WHEN "0100"=> A:=R0-R1;IF A(7 DOWNTO 0)="00000000" THENRC(7 DOWNTO 6):="00";ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01";ELSE RC(7 DOWNTO 6):="10";END IF;WHEN "0110"=> A:=R2-R1;IF A(7 DOWNTO 0)="00000000" THENRC(7 DOWNTO 6):="00";ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01";ELSE RC(7 DOWNTO 6):="10";END IF;WHEN "0111"=> A:=R3-R1;IF A(7 DOWNTO 0)="00000000" THENRC(7 DOWNTO 6):="00";ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01";ELSE RC(7 DOWNTO 6):="10";END IF;WHEN "1000"=> A:=R0-R2;IF A(7 DOWNTO 0)="00000000" THENRC(7 DOWNTO 6):="00";ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01";ELSE RC(7 DOWNTO 6):="10";END IF;WHEN "1001"=> A:=R1-R2;IF A(7 DOWNTO 0)="00000000" THENRC(7 DOWNTO 6):="00";ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01";ELSE RC(7 DOWNTO 6):="10";END IF;WHEN "1011"=> A:=R3-R2;IF A(7 DOWNTO 0)="00000000" THENRC(7 DOWNTO 6):="00";ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01";ELSE RC(7 DOWNTO 6):="10";END IF;WHEN "1100"=> A:=R0-R3;IF A(7 DOWNTO 0)="00000000" THENRC(7 DOWNTO 6):="00";ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01";ELSE RC(7 DOWNTO 6):="10";END IF;WHEN "1101"=> A:=R1-R3;IF A(7 DOWNTO 0)="00000000"THENRC(7 DOWNTO 6):="00";ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01";ELSE RC(7 DOWNTO 6):="10";END IF;WHEN "1110"=> A:=R2-R3;IF A(7 DOWNTO 0)="00000000" THENRC(7 DOWNTO 6):="00";ELSIF A(7)='1' THENRC(7 DOWNTO 6):="01";ELSE RC(7 DOWNTO 6):="10";END IF;WHEN OTHERS=> NULL;END CASE;WHEN Notp => --取反CASE IR(10 DOWNTO 9) ISWHEN "00"=>R0:=Not R0;WHEN "01"=>R1:=Not R1;WHEN "10"=>R2:=Not R2;WHEN "11"=>R3:=Not R3;END CASE;WHEN Clear => --清空IR <= (OTHERS=>'0');PC := (OTHERS=>'0');R0 := (OTHERS=>'0');R1 := (OTHERS=>'0');R2 := (OTHERS=>'0');R3 := (OTHERS=>'0');A := (OTHERS=>'0');MAR <= (OTHERS=>'0');MDR <= (OTHERS=>'0');overflow <= '0';WHEN Absp => --取绝对值CASE IR(10 DOWNTO 9) ISWHEN "00"=>IF(R0(7)='1') THENR0:='0'&R0(6 DOWNTO 0);ELSER0:=R0;END IF;WHEN "01"=>IF(R1(7)='1') THENR1:='0'&R1(6 DOWNTO 0);ELSER1:=R1;END IF;WHEN "10"=>IF(R2(7)='1') THENR2:='0'&R2(6 DOWNTO 0);ELSER2:=R2;END IF;WHEN "11"=>IF(R3(7)='1') THENR3:='0'&R0(6 DOWNTO 0);ELSER3:=R3;END IF;END CASE;WHEN OTHERS => NULL;END CASE;END CASE;END IF;END PROCESS seq;M_address <= MAR;M_data_out <= MDR;Write_Read <= '1' WHEN reset = '1' AND status = 5 AND IR(15 downto 12) = WriteELSE '0' ;END RTL;七．模型机在Quartus II环境下的应用：步骤：1.建立工程：工程名cpu2.编写cpu的VHDL代码，将其添加到工程3.生成cpu的符号图4.建立内存数据的mif文件5.生成16bits的ram6.建立computer的block进行编译7.对computer进行功能模拟8.分析仿真波形八．仿真波形：1）cpu的编译报告2）computer(由cpu和ram组成)的连接图3）功能模拟的波段九．课程设计的总结：通过了这次课程设计我发现自己对cpu的组成与工作有了更深刻的认识。