Parameter VDD AVDD VIO1 VIO2 VIO3 VIO4 VIO5 VBATT VBUS CVDDQ U3TXVDDQ U3RXVDDQ Description Core voltage supply Analog voltage supply GPIF II I/O power domain IO2 power domain IO3 power domain UART/SPI/I2S power domain I C and JTAG supply domain USB voltage supply USB voltage supply Clock voltage supply USB 3.0 1.2 V supply USB 3.0 1.2 V supply
VDD 22uF 0.1uF VDD VBAT 0.01uF 0.1uF VBATT
AVDD 2.2uF 0.1uF
AVDD
VIO1 0.01uF 0.1uF
VIO1
U3TXVDF 0.1uF
VIO2
U3RXVDDQ 22uF 0.1uF
U3RXVDDQ
VIO3 0.01uF 0.1uF
VIO3
CVDDQ 0.1uF VBUS 0.1uF 0.01uF
CVDDQ
VIO4
VIO4 0.01uF 0.1uF
AVSS U3VSS U2AFE U2PLL
VBUS
VIO5
VIO5 0.01uF 0.1uF
Table 1. EZ-USB FX3 Power Domains Description
Max 1.25 1.25 3.6 3.6 3.6 3.6 3.6 6 6 3.6 1.25 1.25
Unit V V V V V V V V V V V V

Document No. 001-70707 Rev. *E
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EZ-USB FX3™ Hardware Design Guidelines and Schematic Checklist
®
Power Modes
EZ-USB FX3 supports the following power modes:

Standby mode (L3): Power supply for the wakeup source and core power must be retained. All other power domains can be turned off/on individually. Core power down mode (L4): Core power is turned off. All other power domains can be turned off/on individually.
Contents
Introduction ....................................................................... 1 Power System ................................................................... 2 Overview ...................................................................... 2 Power Modes ............................................................... 3 Device Supply Decoupling............................................ 3 Inrush Current Consideration and Power Supply Design .............................................................. 4 Clocking ............................................................................ 5 Crystal .......................................................................... 5 Clock ............................................................................ 6 Watchdog Timer ........................................................... 6 GPIF II Interface ................................................................ 6 I2C Interface ...................................................................... 6 Low Performance Peripherals (LPP) ................................. 7 JTAG ............................................................................ 7 2 I S................................................................................. 7 SPI and UART .............................................................. 7 Booting .............................................................................. 7 EMI and ESD Considerations ............................................ 7 FX3 Device Package Dimensions ..................................... 8 Electrical Design Consideration ........................................ 8 USB 3.0 SuperSpeed Design Guidelines ..................... 8 Appendix A – PCB Layout Tips ....................................... 14
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Min 1.15 1.15 1.7 1.7 1.7 1.7 1.15 3.2 4.0 1.7 1.15 1.15
VSS
Typical 1.2 V typical 1.2 V typical 1.8, 2.5 and 3.3 V typical 1.8, 2.5 and 3.3 V typical 1.8, 2.5 and 3.3 V typical 1.8, 2.5 and 3.3 V typical 1.2, 1.8, 2.5 and 3.3 V typical 3.7 V typical 5 V typical 1.8, 3.3 V typical 1.2 V typical 1.2 V typical

Normal mode: This is the full-functional operating mode. In this mode the internal CPU clock and the internal PLLs are enabled.
Introduction
The Cypress EZ-USB FX3 has an integrated USB 3.0 and USB 2.0 physical layer (PHY), and a fully configurable, parallel, general programmable interface called GPIF II, which can connect to an external processor, ASIC, or FPGA. EZ-USB FX3 enables data transfers up to 320 MBps from GPIF II to the USB interface. To successfully add this high throughput pipe to a system, a developer has to consider a number of critical items when designing the system. Because of the packaging and high-performance characteristics of the EZ-USB FX3 device, you should follow the guidelines for trace width, stack up, and other layout considerations to make sure the system will perform as expected. A reference schematic for the EZ-USB FX3 DVK is available at CYUSB3KIT-001 EZ-USB® FX3™.
AN70707 EZ-USB® FX3™ Hardware Design Guidelines and Schematic Checklist