十进制计数器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS PORT (CLK,RST,EN : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT10; ARCHITECTURE behav OF CNT10 IS BEGIN PROCESS(CLK, RST, EN) VARIABLE BEGIN IF RST = '1' THEN =>'0') ; --计数 ELSIF CLK'EVENT AND CLK='1' THEN IF EN = '1' THEN IF CQI < 9 THEN --允许计数, ELSE --大于 9， END IF; END IF; END IF; IF CQI = 9 THEN COUT <= '1'; --计数大 于 9，输出进位信号 ELSE COUT <= '0'; --将计数值向端口 END IF; CQ <= CQI; 输出 END PROCESS; END behav; CQI := (OTHERS =>'0'); CQI := CQI + 1; CQI := (OTHERS CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);
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六十进制计数器源程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt60 is port(clk,rst,en:in std_logic; cq:out std_logic_vector(7 downto 0); cout:out std_logic); end cnt60; architecture behav of cnt60 is begin process(clk,rst,en) variable cqi:std_logic_vector(7 downto 0); begin if rst='1' then cqi:=(others=>'0'); elsif clk'event and clk='1' then if en='1' then if cqi<59 then cqi:=cqi+1; else cqi:=(others=>'0'); end if; end if; end if; if cqi=59 then cout<='1'; else cout<='0'; end if; cq<=cqi; end process; end behav;