R 55
47 k,NC
G ND
+ C 70 4.7uF/10V
C 69 0.1uF
+ C 68 4.7uF/10V
C 67 0.1uF
0.1uF
ASIX ELECTRONICS CORPORATION Title AX88178 Demo Board-F Size C
5 4 3 2
Document Number AX88178 Demo Board-F - AX88178 Monday, May 18, 2009
127 124 119 100 98 87 81 75 40 25 18 17 7 69 67 63 60 55 54 50 38 33 29
GPIO0 RGMII_EN
R 37 R 71 R 68 R 34 R 35
3 3K,NC 3 3K,NC 4 .7K,NC 47K 4 7K,NC 4 7k 4 7k 47K 4.7K J1 C ON 2
5
4
3
2
1
/3/ /3/ /3/ /2/ /3/
D
USB_5V U S B_GND MAC_VDD33
USB_5V U S B_GND MAC_VD D33
Note: 1.Please refer to AX88178 USB-to-Gigabit Ethernet Application Design Note for more AX88178 PCB layout design notes. 2.Please contact ASIX Support (support@) to get AX88178 EEPROM User Guide for more details about AX88178 EEPROM setting.
R 67 47K
G ND
G ND
3.Please deliver us your AX88178 schematic and your AX88178 EEPROM data file for further review.
NC NC NC NC NC NC NC NC RX_CLK RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 RX_DV RX_ER C OL C RS TX_CLK GTX_CLK_T TXC_T TXD7_T TXD6_T TXD5_T TXD4_T TXD3_T TXD2_T TXD1_T TXD0_T TX_EN_T TX_ER_T MDIO M DC_T MD INT
Internal regulator 3.3V power input. Internal regulator 2.5V power output.
INT_R EG
3.3V to 2.5V Regulator enable
G ND
MAC_VDD33
GPIO1
R 38 R 39 R 63 R 36
R1 39K 3 C1 0.1uF
NC NC NC NC NC NC NC
62 61 56 92 93 94 95 96
R4 USB_5V MAC_VDD 33A G ND J2 U SB-CON 6 R6 R 62 R 49 R 33
39.0 39.0 4.7K 1.5K 12.1K
4 3 S
1 2
GND VDD5 D+ D-
4 1 3 2
104 114 113 112 111 110 109 108 107 105 106 116 115 102 91 90 76 77 78 79 82 83 84 85 89 88 120 121 117
R 21 R 20
22 22
GTX_CLK TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 TX_EN TX_ER
C 19 12pF
USBACT
D2
L ED O
L ED1
R 25
330
MAC_VD D33
USB High Speed & Transfer LED USB Full Speed LED
U SBSPD
D1
L ED G
L ED2
R 24
330
GND GND GND GND GND GND GND GND GND GND GND GND GND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND
Pin To Configuration Register Mapping
PIN CONFIG0 CONFIG1 CONFIG2 CONFIG3 CONFIG4 CONFIG5 CONFIG6 BIT [2] PHYADR[2] ENA_PAUSE ANEG[3] ANEG[0] MODE[2] DIS_FC SEL_BDT BIT [1] PHYADR[1] PHYARD[4] ANEG[2] ENA_XC MODE[1] DIS_SLEEP INT_POL BIT [0] PHYADR[0] PHYADR[3] ANEG[1] DIS_125 MODE[0] MODE[3] 75/50 OHM 000 111 111 111 011 111 111 010 110 010 011
/2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ /2/ GTX_CLK : GMII 125MHZ clock output. TXC : RGMII 125MHZ clock output.
C 96 0.47uF,NC
XC61G2002 R 74 0, NC
000 111 111 111 110 011 010 111 011 111 010
LED_LINK100 Default use R57, don't use R56&R58&R59 . Default use R40, don't use R41 LED_LINK1000 LED_DUPLEX LED_RX LED_TX V SS
U1 VSS VIN VOUT 2 1
R2 47K
VDD3
MAC_VDD33
AVDD3
MAC_VDD33A
GPIO2 RX_ER F OR CEF#
RESET#
C 37 0.1uF
C 29 0.1uF
C 56 0.1uF
C 89 0.1uF
C 38 0.1uF
C 33 0.1uF
C 41 0.1uF
D
BIT[2:0]
111 110 101 100 011 010 001 000
LED_LINK10
D9 1N4148,NC 3 U 8, NC VSS 1 R 77 4.7K,NC PH Y_ Rst#
R 78
D
3 9K,NC
VIN VOUT 2 C O NFIG4 C O NFIG5 C O NFIG6
C 52 0.1uF
Force USB Full Speed
S1 4 .7K.NC 2 1 SW
XC61G2802
EXTWAKE#
R 32 C 27
0 .1uF,NC G ND
VDD2 & VDDK & AVDDK
MAC_VDD33
A
L4 SBK160808T-110Y-S
11 ohm@100MHz
1
R ev 2.12 Sheet 1 of 4
Date:
5
4
3
2
1
Байду номын сангаас
Pin To Constant Mapping
PIN
VDDO
PH Y_ VDD25 C O NFIG0 C O NFIG1 C O NFIG2 C O NFIG3 R 42 R 43 R 44 R 56 R 57 R 58 R 59 R 40 R 41 R 45 R 46 0 0 0 0 0 0 0 0 0 0 0 G ND PH Y _VDD25 PH Y _VDD25 PH Y _VDD25 LED_LIN K10 LED_D UPLEX LED_RX PH Y _VDD25 LED_D UPLEX PH Y _VDD25 LED_RX
MAC_VDD33A
MAC_VDD25
DB
R 72
4 7k
MAC_VD D25
A
PR ST# C 36 C 34 0.1uF C 93 0.1uF C 77 0.1uF C 57 0.1uF C 76 0.1uF C 73 0.1uF C 42 0.1uF C 60 0.1uF C 66 0.1uF C 72 0.1uF C 75 0.1uF C 91 0.1uF C 92 0.1uF
AX88178
RX_CLK RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 RX_DV RX_ER COL CRS TX_CLK GTX_CLK TXC TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 TX_EN TX_ER MDIO MDC MDINT
C 31 0.1uF
C
DB E ECK E ECS E EDI E EDO R5 22 EECK_T
XIN125M RESET_N EXTWAKEUP_N GPIO2 GPIO1 GPIO0 PHYRST_N RGMII_EN/NC FORCEFS_N LED USB_SPEED_LED TESTSPEEDUP HS_TEST_MODE SCAN_TEST SCAN_ENABLE CLK60EXT CLKSEL DB EECK EECS EEDI EEDO VDD3 VDD3 VDD3 VDD3 VDD3 AVDD3 AVDD3 AVDD3 VDDAH GNDAH V25 INT_REGULATOR_EN