版图设计实验报告课程名称：集成电路版图设计姓名：学号；专业；电子科学与技术教师；老师目录（一）实验目的 (3)（二）实验步骤 (4)1，搭建环境····································································································2，运用ic6151···························································································3，作图···········································································································4，Run DRC··························································································5，画原理图···························································································6，Run LVS········································································································（三）实验总结·················································································································（一）实验目的1、熟悉Linux系统基本命令并学会使用；2、掌握使用Cadence Virtuoso版图编辑软件进行模拟IC 版图布局设计；3、Cadence-Virtuoso Layout Editor是一种基于Linux系统的EDA工具；（1）熟练使用快捷键；R;画矩形， ESC；取消任务， delete；除去、U；撤销， shift + f;变繁体 k；测距离C；复制， s;改变形状 p;双沟道 L创建标识等等；(2) 画线和贴片；横----A2纵----A1M1-M24、学会用Cadence搭建网表即如何构建电路，并对电路图进行检查和验证；5、为了从电路图提取网表，用于后续layout的LVS检查验证做准备；6、学习对电路模块的认识。