1. 具有CLK，Q端口的简单加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK : IN STD_LOGIC;Q : OUT INTEGER RANGE 15 DOWNTO 0);END;ARCHITECTURE behav OF CNT4 ISSIGNAL D,Q1 : INTEGER RANGE 15 DOWNTO 0;BEGINPROCESS (CLK)BEGINIF CLK'EVENT AND CLK='1'THEN Q1<=D;END IF;END PROCESS;D<=Q1+1;Q<=Q1;END behav;2. 具有异步清零aclr，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK,ACLR : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 : STD_LOGIC_VECTOR(15 DOWNTO 0);BEGINPROCESS (CLK,ACLR)BEGINIF ACLR='0' THENQ1<=(OTHERS=>'0');ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END PROCESS;Q<=Q1;END behav;3. 具有同步清零sclr，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT ( CLK,SCLR : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 : STD_LOGIC_VECTOR(15 DOWNTO 0);BEGINPROCESS (CLK,SCLR)BEGINIF CLK'EVENT AND CLK='1' THENIF SCLR='1' THENQ1<=(OTHERS=>'0');ELSEQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;4. 具有异步置位apre，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE)BEGINIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END PROCESS;Q<=Q1;END behav;5. 具有同步置位spre，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;SPRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,SPRE)BEGINIF CLK'EVENT AND CLK='1' THENIF SPRE='1' THENQ1<="0001";ELSEQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;6. 具有异步清零aclr，异步置位apre，CLK，Q端口的加法计数器，要程序和最后的RTL 图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ACLR:IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE,ACLR)BEGINIF ACLR='1' THENQ1<="0000";ELSEIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;7. 具有同步使能ENB，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ENB :IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,ENB)BEGINIF CLK'EVENT AND CLK='1' THENIF ENB='1' THENQ1<=Q1+1;END IF;END IF;END PROCESS;Q<=Q1;END behav;8. 具有异步清零aclr，异步置位apre，同步使能ENB，CLK，Q端口的加法计数器，要程序和最后的RTL图；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT4 ISPORT(CLK :IN STD_LOGIC;ACLR:IN STD_LOGIC;ENB :IN STD_LOGIC;APRE:IN STD_LOGIC;Q :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END;ARCHITECTURE behav OF CNT4 ISSIGNAL Q1 :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,APRE,ACLR,ENB)BEGINIF ACLR='1' THENQ1<="0000";ELSEIF APRE='1' THENQ1<="0001";ELSIF CLK'EVENT AND CLK='1' THENIF ENB='1' THENQ1<=Q1+1;END IF;END IF;END IF;END PROCESS;Q<=Q1; END behav;。