实验报告学生姓名学号指导教师日期实验项目名称：秒表计时电路报告评分：教师签字：一、设计思路概述输入信号为4位状态切换位加上50MHz的时钟，状态分别为保持、清零、运行和置位，需要一个时钟同步状态机加以控制。
输出信号为6位数码管，分别显示秒表的时、分、秒。
每一位数码管都采用不同的时钟信号进行控制，可以通过系统时钟进行不断地分频得到所需求的时钟信号。
二、总体设计框图及详细说明三、模块设计框图、相关时序状态机设计时钟分频clk10ms → clk100ms → clk1s → clk10s → clk1min → clk10min → clk1h分频单元采用六分频和十分频。
50MHz时钟信号到100Hz时钟信号的分频采用500000分频。
四、代码及必要注释//6进制分频计数器module count6(rst, clk, clkout, counter);input rst;input clk;output reg clkout;output reg [3:0]counter;always @(negedge clk or negedge rst) beginif (~rst) begin clkout <= 0; counter <= 0; endelse if (counter == 4'b0010) beginclkout <= ~clkout;counter <= counter+4'b0001;endelse if (counter == 4'b0101) beginclkout <= ~clkout;counter <= 0;endelse begincounter <= counter + 4'b0001;endendendmodule//10进制分频计数器module count10(rst, clk, clkout, counter);input rst;input clk;output reg clkout;output reg [3:0]counter;always @(negedge clk or negedge rst) beginif (~rst) beginclkout <= 0;counter <= 0;endelse if (counter == 4'b0100) beginclkout <= ~clkout;counter <= counter + 4'b0001;endelse if (counter == 4'b1001) beginclkout <= ~clkout;counter <= 0;endelse begincounter <= counter + 4'b0001;endendendmodulemodule parkerxie(key, ledr, ledg, hex, clk);input [3:0] key;input clk;output reg [17:0] ledr;output reg [7:0] ledg;output [55:0] hex;wire clear;wire start;wire stop;wire hold;assign clear = key[0];assign start = key[1];assign stop = key[2];assign hold = key[3];reg [19:0] clk10msreg;reg clk10ms;wire clk100ms;wire clk1s;wire clk10s;wire clk1min;wire clk10min;wire clk1h;reg [1:0] state;parameter idlestate = 2'b00, prestate = 2'b01, holdstate = 2'b10,runstate = 2'b11;reg rst;reg rst10ms;reg [2:0] displayreg;wire [3:0] timeout [7:0];reg [6:0] segcode[7:0];assign hex = {segcode[7],segcode[6],segcode[5],segcode[4],segcode[3], segcode[2],segcode[1],segcode[0]};//状态机always @(negedge clk or negedge clear) beginif (~clear) beginstate <= idlestate; rst <= 0; rst10ms <= 0;endelse begincase (state)idlestate: beginif (~start) beginstate <= prestate;rst <= 0;rst10ms <= 0;endelse beginstate <= idlestate;endendprestate: beginstate <= runstate;rst <= 1;rst10ms <= 1;endholdstate: beginif (~start) beginstate <= runstate;rst <= 1;rst10ms <= 1;endelse if (~stop) beginstate <= idlestate;rst <= 1;rst10ms <= 0;endelse beginstate <= holdstate;endendrunstate: beginif (~hold) beginstate <= holdstate;rst <= 1;rst10ms <= 0;endelse if (~stop) beginstate <= idlestate;rst <= 1;rst10ms <= 0;endelse beginstate <= runstate;endenddefault: state <= state;endcaseendend// 50MHz 100Hzalways @(negedge clk or negedge rst10ms) beginif (~rst10ms) beginclk10ms <= 0;clk10msreg <= 0;endelse if (clk10msreg == 249999) beginclk10ms <= ~clk10ms;clk10msreg <= 0;endelse beginclk10msreg <= clk10msreg + 16'b1;endend// 各级分频count6 min10counter(rst, clk10min, clk1h, timeout[7]); count10 min1counter (rst, clk1min, clk10min, timeout[6]); count6 sec10counter(rst, clk10s, clk1min, timeout[5]); count10 sec1counter (rst, clk1s, clk10s, timeout[4]); count10 ms100counter(rst, clk100ms, clk1s, timeout[3]); count10 ms10counter (rst, clk10ms, clk100ms, timeout[2]); assign timeout[1] = 4'b1111;assign timeout[0] = 4'b1111;//显示译码输出电路always @(negedge clk or negedge rst) beginif (~rst) begindisplayreg <= 3'b000;segcode[0] <= 7'b1111111;segcode[1] <= 7'b1111111;segcode[2] <= 7'b1000000;segcode[3] <= 7'b1000000;segcode[4] <= 7'b1000000;segcode[5] <= 7'b1000000;segcode[6] <= 7'b1000000;segcode[7] <= 7'b1000000;endelse begincase (timeout[displayreg])0: segcode[displayreg] <= 7'b1000000;1: segcode[displayreg] <= 7'b1111001;2: segcode[displayreg] <= 7'b0100100;3: segcode[displayreg] <= 7'b0110000;4: segcode[displayreg] <= 7'b0011001;5: segcode[displayreg] <= 7'b0010010;6: segcode[displayreg] <= 7'b0000010;7: segcode[displayreg] <= 7'b1011000;8: segcode[displayreg] <= 7'b0000000;9: segcode[displayreg] <= 7'b0010000;default: segcode[displayreg] <= 7'b1111111;endcasedisplayreg <= displayreg + 3'b1;endend//流水灯always @(negedge clk1s or negedge rst) begin if (~rst)ledg <= 8'b0;else if (ledg == 8'b0)ledg <= {ledg[6:0], 1'b1};elseledg <= {ledg[6:0], ledg[7]};endalways @(negedge clk100ms or negedge rst) begin if (~rst)ledr <= 18'b0;else if (ledr == 18'b0)ledr <= {ledr[16:0], 1'b1};elseledr <= {ledr[16:0], ledr[17]};endendmodule。