3,4
5,4,3
6,5,4 X =< 3.80 SODIMM
5,4,3
38h
70h 01h 04h 00h 07h
38h
Analysis probe not installed, FET switch external not enable Supports weak driver, 50Ohm ODT, PASR 3.75ns +/-0.5ns 5.0ns +/-0.6ns 12.5ns 3.0ns +/- 0.45ns 3.75ns +/-0.5ns 15ns 7.5ns 12.5ns 15ns 45ns 1GB 0.175ns 0.25ns 0.05ns 0.125ns 0.20ns 0.27ns 0.10ns 0.17ns 15ns 0.22ns 0.25ns 0.37ns 0.35ns 0.47ns 0.15ns 0.27ns 17h 25h 05h 12h 40ns 32h 3.75ns +/-0.5ns 5.0ns +/-0.6ns 5.0ns +/-0.6ns 3Dh 50h 50h 60h 32h 3Dh 50h 30h 45h
Function described
Internal write to read command delay(=tWTR) Internal read to precharge command delay(=tRTP) Memory analysis probe characteristics Extension of Byte41 tRC and Byte42 tRFC DDR2 SDRAM device min. active to active/auto refresh time(=tRC) DDR2 SDRAM device min. auto-refresh to active/auto-refresh command period(=tRFC) DDR2 SDRAM device max. device cycle time(=tCK max) DDR2 SDRAM device max. skew for DQS and associated DQ signals(=tDQSQ max) DDR2 SDRAM read data hold skew factor(=tQHS) PLL Relock Time DT in SPD High Temp. Self Refresh IDD in SPD SPD data revision code Checksum for Bytes 0 ~ 62 Manufacturer JEDEC ID code ......Manufacturer JEDEC ID code Manufacturing location Manufacturer Part #(Memory module) Manufacturer part # (DIMM configuration) Manufacturer part # (Data bits & Module type) ......Manufacturer part # (Data bits & Module type) ......Manufacturer part # (Data bits & Module type) Manufacturer part # (Operating Voltage) Manufacturer part # (Module depth) Manufacturer part # (Module depth) Manufacturer Part # (Refresh. # of rows in comp. & interface) Manufacturer part # (composition component) Manufacturer part # (Component revision) Manufacturer part # (Package type) Manufacturer part # (PCB revision) Manufacturer part # (Hyphen) Manufacturer part # (Power) Manufacturer part # (Minimum cycle time) Manufacturer part # (Minimum cycle time) Manufacturer part # (T.B.D) Manufacturer Revision Code(For PCB) Manufacturer Revision Code (For component) Manufacturing Date (Year) Manufacturing date (week) Assembly serial # Manufacturer specific data(may be used in future) Open for customer use 1 . This will typically be programmed as 128 Bytes. 2 . This will typically be programmed as 256 Bytes. 3 . From Datasheet
Hex Value CCC CE7 CF7 CE6
80h 08h 08h 0Eh 0Ah 61h 40h 00h 05h 30h 45h 00h 82h 08h 00h 00h 0Ch 08h 3Dh 50h 50h 60h
CD5
CD5
CCC
Note
1 2
+/-0.45ns +/-0.5ns Non parity/ECC 7.8us x8 N/A 4,8 8 banks
SERIAL PRESENCE DETECT
M470T5663QZ3-CE7/CF7/CE6/CD5/CCC
Organization :256M x 64 Composition :128M x 8 * 16ea Used component part # :K4T1G084QQ-HCE7/F7/E6/D5/CC # of rows in module Row :2 # of banks in component :8 banks Feature :30mm height & double sided component Refresh :8K/64ms Bin Sort : E7(DDR2-800@CL=5), F7(DDR2-800@CL=6), E6(DDR2-667@CL=5), D5(DDR2-533@CL=4), CC(DDR2-400@CL=3) Contents :
Byte #
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Function described
# of Serial PD Bytes written during module production Total Number of SPD memory device Fundameatal memory type # of row address on this assembly # of column address on this assembly # of module rows on this assembly Data width of this assembly Reserved Voltage interface level of this assembly DDR2 SDRAM cycle time at Max. Supported CAS latency=X DDR2 SDRAM Access time from clock at CL=X DIMM configuration type (address&command parity, data parity, ECC) Refresh rate Primary DDR2 SDRAM width Error checking DDR2 SDRAM data width Reserved DDR2 SDRAM device attributes : Burst lengths supported DDR2 SDRAM device attributes : # of banks on each DDR2 SDRAM device DDR2 SDRAM device attributes : CAS latency supported DIMM Mechanical Characteristics DIMM type information DDR2 SDRAM module attributes DDR2 SDRAM device attributes : General DDR2 SDRAM cycle time at CL= X-1 DDR2 SDRAM access time from clock at CL= X-1 DDR2 SDRAM cycle time at CL= X-2 DDR2 SDRAM access time from clock at CL= X-2 Minimum row precharge time(=tRP) Minimum row active to row active delay(=tRRD) Minimum RAS to CAS delay(=tRCD) Minimum active precharge time(=tRAS) Module rank density Command and address setup time before clock(=tIS) Command and address hold time after clock(=tIH) Data input setup time before strobe(=tDS) Data input hold time after strobe(=tDH) Write recovery time(=tWR)