一位全加器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;entity adder isport(a,b,cin:in std_logic;co,so:out std_logic);end adder;architecture Behavioral of adder issignal temp1,temp2:std_logic;begintemp1<= a xor b;temp2<= temp1 and cin;so<= temp1 xor cin;co<= temp2 OR (a AND b);end Behavioral;四位全加器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;entity counter10 isport(a,b:in std_logic_vector(3 downto 0);cin:in std_logic;co:out std_logic;so:out std_logic_vector(3 downto 0));end counter10;architecture Behavioral of counter10 issignal carry:std_logic_vector(0 to 2);component adderport(a,b,cin:in std_logic;co,so: out std_logic);end component;beginu0:adder port map(a(0),b(0),cin,carry(0),so(0));u1:adder port map(a(1),b(1),carry(0),carry(1),so(1)); u2:adder port map(a(2),b(2),carry(1),carry(2),so(2)); u3:adder port map(a(3),b(3),carry(2),co,so(3));end Behavioral;60进制计数器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;entity counter60 isport(clk, clr, en: in std_logic;q1,q2: out std_logic_vector(3 downto 0);co: out std_logic);end counter60;architecture Behavioral of counter60 issignal temp:std_logic;component counter6port ( clk, clr, en: in std_logic;q: out std_logic_vector(3 downto 0);co:out std_logic);end component;component counter10port ( clk, clr, en: in std_logic;q: out std_logic_vector(3 downto 0);co: out std_logic);end component;beginu1:counter10 port map(clk,clr,en,q1,temp);u2:counter6 port map(temp,clr,en,q2,co);end Behavioral;6进制计数器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;entity counter6 isport(clk, clr, en: in std_logic;q: out std_logic_vector(3 downto 0);co:out std_logic);end counter6;architecture Behavioral of counter6 issignal temp: std_logic_vector(3 downto 0);beginq(0)<=temp(0);q(1)<=temp(1);q(2)<=temp(2);q(3)<=temp(3);process(clr, clk, en)beginif (clr='0') thentemp<=(others=>'0');co <= '0';elsif(clk'event and clk='1') thenif(en='1') thenif(temp="0101") thenco<='1';temp<="0000";else temp<=temp+'1';co<='0';end if;end if;end if;end process;end Behavioral;6进制计数器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the declarations that are-- provided for instantiating Xilinx primitive components. --library UNISIM;--use UNISIM.VComponents.all;entity counter10 isport(clk, clr, en: in std_logic;q: out std_logic_vector(3 downto 0);co: out std_logic);end counter10;architecture Behavioral of counter10 issignal temp: std_logic_vector(3 downto 0);beginq(0)<=temp(0);q(1)<=temp(1);q(2)<=temp(2);q(3)<=temp(3);process(clr, clk, en)beginif (clr='0') thentemp<=(others=>'0');co <= '0';elsif(clk'event and clk='1') thenif(en='1') thenif(temp="1001") thenco<='1';temp<="0000";else temp<=temp+'1';co<='0';end if;end if;end if;end process;end Behavioral;作业：1、如果输出端口q定义成：q: buffer integer range 3 downto 0;还需要内部信号temp 吗？程序怎样修改？答：不需要内部信号。

程序如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY counter10 ISPORT(clk,clr,en : IN STD_LOGIC;q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);co : OUT STD_LOGIC);END counter10;ARCHITECTURE behav OF counter10 ISBEGINPROCESS(clk,clr,en)BEGINIF(clr='1') THENq <= "0000";ELSEIF(en='1') THENIF(clk'EVENT AND clk='1') THENIF(q = "1001") THENq <= "0000";co <= '1';ELSEq <= q + 1;co <= '0';END IF;END IF;END IF;END IF;END PROCESS;END behav;作业：2、将内部信号temp改成局部变量temp可以吗?程序怎样修改？答：可以。