译码器的设计architecture dec_behave of e1 isSigna lsel : std_logic_vector( 0 to 3) ; beginsel(0) <= en ; sel(1) <= a(0) ; sel(2) <= a(1) ; sel(3) <= a(2) ;with sel selecty <= "00000001" when "1000","00000010" when "1001","00000100" when "1010","00001000" when "1011","00010000" when "1100","00100000" when "1101","01000000" when "1110","10000000" when "1111","00000000" when others ;end dec_behave ;编码器的设计library IEEE；entity encoder83 is port( ind: in std_logic_vector(7 downto 0)；outd: out std_logic_vector(2 downto 0)); end ;architecture behave of encoder83 isbegin process (ind)beginif ind (7) = …1' then outd<= "111";elsif ind (6) = …1' then outd<= "110";elsif ind (5) = …1' then outd<= "101";elsif ind (4) = …1' then outd<= "100";elsif ind (3)= …1' then outd<= "011";elsif ind (2) = …1' then outd<= "010";elsif ind (1) = …1' then outd<= "001";elsif ind (0) = …1' then outd<= "000";else outd<= "000";end if;end process; end behave;数据选择器的设计LIBRARY IEEE ; ……；ENTITY E3 ISPORT (A,B,C,D : IN STD_LOGIC_VECTOR( 3 DOWNTO 0) ; S : IN STD_LOGIC_VECTOR( 0 TO 1)；Z:OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 )）；END ；ARCHITECTURE CONC_BEHAVE OF E3 ISBEGINZ<= A WHEN S="00" ELSEB WHEN S="01" ELSEC WHEN S="10" ELSED WHEN S="11" ELSE"0000" ；END CONC_BEHAVE ；比较器：设计八位比较器，相等时输出为1，否则输出为0library ieee；entity compare isport (a,b: in std_logic_vector (7 downto 0);y: out std_logic);end compare;architecture behave of compare isbeginprocesss (a,b)Beginif (a=b) then y<='1';else y<='0';end if; end process; end behave;求补器：求补器的输入信号为a（7..0），输出信号为b（7..0），设a（7）和b（7）为符号位。

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity complement isport(a: in std_logic_vector (7 downto 0);b: out std_logic_vector (7 downto 0));end complement;architecture behave of complement isbegin process (a)beginif (a (7) ='0' ) then b<=a; else b<='1'& (not a (6 downto 0) + '1' ); end if;end process;end behave;单向总线缓冲器的设计LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY e7 IS port(enable : IN STD_LOGIC;datain: IN STD_LOGIC_VECTOR(7 DOWNTO 0);dataout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END; ARCHITECTURE bhv OF e7 ISBEGINPROCESS(enable,datain)BEGINIF enable = '1' THEN dataout <= datain ;ELSE dataout <="ZZZZZZZZ" ;END IF ; END PROCESS; END bhv;双向总线缓冲器的设计library ieee;……ENTITY e8 ISport ( en,dr : in std_logic;a,b : inout std_logic_vector(7 downto 0));END;ARCHITECTURE bhv OF e8 ISsignal aout,bout :std_logic_vector(7 downto 0);beginprocess(a,en,dr)BEGIN if ((en = '0')and(dr='1')) then bout <= a ;else bout <="ZZZZZZZZ" ;end if ;b<=bout;END process;process(b,en,dr)BEGINif ((en = '0')and(dr='0')) thenaout <= b ;else aout <="ZZZZZZZZ" ; end if ; a<=aout;END process; END bhv;同步复位信号的VHDL描述：process (复位信号名，时钟信号名)beginif （时钟信号变化条件）thenif (复位信号变化条件) then状态复位语句；else顺序语句；end if;end if;end process;异步复位信号的VHDL描述：process (复位信号名，时钟信号名)beginif (复位信号变化条件) then状态复位语句；elsif （时钟信号变化条件）then顺序语句；end if;end process;8D锁存器使能信号en=1时，数据锁存，否则数据保持。

library ieee;……；entity d_latch isport (en : in std_logic;d : in std_logic_vector (7 downto 0);q : out std_logic_vector (7 downto 0));end d_latch;architecture behave of d_latch isbeginprocess (en, d) beginif en='1' then q<=d;end if;end process;end behave;设计四位D触发器，具有异步清零CLR和置位PRN、同步使能EN控制功能。

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY sh1 isPORT(CLK,CLR,PRN,EN : IN STD_LOGIC;D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END ;ARCHITECTURE a OF sh1 IS BEGIN PROCESS (CLR,PRN,CLK,EN) BEGIN IF CLR='1' THENQ<=(OTHERS=>'0');ELSIF PRN='1' THENQ<=(OTHERS=>'1');ELSIF RISING_EDGE(CLK) THEN IF EN='1' THENQ <= D;END IF;END IF;END PROCESS;END a;设计4bit的移位寄存器，具有左移一位或右移一位，并行输入和同步复位的功能。

Library ……；entity shifter isport (data: in std_logic_vector (3 downto 0);left_da, right_da, reset, clk : in std_logic;mode : in std_logic_vector (1 downto 0); qout: buffer std_logic_vector (3 downto 0));end shifter;architecture behave of shifter isbegin processbeginwait until rising_edge (clk);if (reset = '1' ) then qout<= "0000";else case mode iswhen “01” =>qout <= right_da & qout ( 3 downto 1);when "10" =>qout <=qout (2 downto 0) & left_da;when "11" =>qout <=data;when others =>null;end case; end if; end process; end behave;60进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cout60_v isport(clrn,ldn,en,clk : in std_logic;da : in std_logic_vector(3 downto 0);db : in std_logic_vector(2 downto 0);qa : out std_logic_vector(3 downto 0);qb : out std_logic_vector(2 downto 0);rco : out std_logic);end cout60_v;architecture a of cout60_v isbeginprocess (clk)variable tmpa :std_logic_vector(3 downto 0);variable tmpb :std_logic_vector(2 downto 0);beginif clrn='0' then tmpb := "000"; tmpa := "0000";elseif (clk'event and clk='1') thenif ldn='0' then tmpa :=da; tmpb:=db; elsif en='1' thenif tmpa="1001" then tmpa:="0000";if tmpb="101" then tmpb:="000";else tmpb:= tmpb+1;end if;else tmpa := tmpa+1;end if; end if;end if;end if;qa <= tmpa; qb <= tmpb;rco<= tmpb(0) and tmpb(2) and tmpa(0) and tmpa(3) and en;end process ; end a;用D触发器构成四位移位寄存器。