下面给出实现数字时钟设计的Verilog代码
module top(inc_hour,sub_hour,inc_min,sub_min,rst,clk,sel,q); input inc_hour,sub_hour,inc_min,sub_min;
input rst,clk;
output reg [2:0] sel;
output reg [6:0] q;
reg [9:0] scan;
reg [2:0] scan_clk;
reg div_clk;
reg [19:0] counter_clk;
reg [3:0] sec_counter1,sec_counter2;
reg [3:0] min_counter1,min_counter2;
reg [3:0] hour_counter1,hour_counter2;
always @ (negedge rst or posedge clk)
begin
if(~rst)
begin
counter_clk<=20'h00000;
div_clk<=1'b0;
end
else
begin
if(counter_clk==20'h7a11f)
begin
counter_clk<=20'h00000;
div_clk<=~div_clk;
end
else counter_clk<=counter_clk+1;
end
end
always @(negedge rst or posedge div_clk)
begin
if(~rst)
begin
sec_counter1<=4'h0;
sec_counter2<=4'h0;
min_counter1<=4'h0;
min_counter2<=4'h0;
hour_counter1<=4'h0;
hour_counter2<=4'h0;
end
else
if(inc_min==1'b0) begin
if(min_counter1==4'h9) begin min_counter1<=4'h0;
if(min_counter2==4'h5)
min_counter2<=4'h0;
else
min_counter2<=min_counter2+1; end
else
min_counter1<=min_counter1+1; end
else if(sub_min==4'b0) begin
if(min_counter1==4'h0) begin min_counter1<=4'h9;
if(min_counter2==4'h0)
min_counter2<=4'h5;
else
min_counter2<=min_counter2-1; end
else
min_counter1<=min_counter1-1; end
else if(inc_hour==4'b0) begin
if(hour_counter2==4'h2) begin
if(hour_counter1==4'h3) begin hour_counter2<=4'h0;
hour_counter1<=4'h0;
end
else
hour_counter1<=hour_counter1+1; end
else begin
if(hour_counter1==4'h9) begin hour_counter1<=4'h0;
hour_counter2<=hour_counter2+1; end
else
hour_counter1<=hour_counter1+1; end
end
else if(sub_hour==1'b0) begin
if(hour_counter1==1'b0) begin
if(hour_counter2==1'b0) begin
hour_counter1<=4'h3;
hour_counter2<=4'h2;
end
else begin
hour_counter2<=hour_counter2-1; hour_counter1<=4'h9;
end
end
else
hour_counter1<=hour_counter1-1; end
else begin
if(sec_counter1>=4'h9) begin
sec_counter1<=4'h0;
if(sec_counter2>=4'h5) begin
sec_counter2<=4'h0;
if(min_counter1>=4'h9) begin min_counter1<=4'h0;
if(min_counter2>=4'h5) begin min_counter2<=4'h0;
if(hour_counter2==4'h2) begin
if(hour_counter1==4'h3) begin hour_counter1<=4'h0;
hour_counter2<=4'h0;
end
else
hour_counter1<=hour_counter1+1; end
else begin
if(hour_counter1==4'h9) begin hour_counter1<=4'h0;
hour_counter2<=hour_counter2+1; end
else
hour_counter1<=hour_counter1+1; end
end
min_counter2<=min_counter2+1; end
min_counter1<=min_counter1+1; end
sec_counter2<=sec_counter2+1; end
sec_counter1<=sec_counter1+1;
end
end
always @(negedge rst or posedge clk) begin
if(~rst) scan_clk<=3'b000;
else
begin
if(scan_clk==3'b101) scan_clk<=3'b000; else scan_clk<=scan_clk+1;
end
end
always @(scan_clk)
begin
case (scan_clk)
3'b000 :
begin
q<=disp(sec_counter1);
sel<=3'b000;
end
3'b001 :
begin
q<=disp(sec_counter2);
sel<=3'b001;
end
3'b010 :
begin
q<=disp(min_counter1);
sel<=3'b010;
end
3'b011 :
begin
q<=disp(min_counter2);
sel<=3'b011;
end
3'b100 :
begin
q<=disp(hour_counter1);
sel<=3'b100;
end
3'b101 :
begin
q<=disp(hour_counter2);
sel<=3'b101;
end
default : ;
endcase
end
function[6:0] disp;
input[3:0] a;
case (a)
4'h0 : disp=7'b0111111; 4'h1 : disp=7'b0000110; 4'h2 : disp=7'b1011011; 4'h3 : disp=7'b1001111; 4'h4 : disp=7'b1100110; 4'h5 : disp=7'b1101101; 4'h6 : disp=7'b1111101; 4'h7 : disp=7'b0000111; 4'h8 : disp=7'b1111111;
4'h9 : disp=7'b1101111; default : disp=7'b1111111; endcase
endfunction endmodule。