8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation DIP14 package SO14, (T)SSOP14 and DHVQFN14 packages
Fig 5.
Pin configuration DHVQFN14
6.2 Pin description
Table 2. Symbol 1A to 6A 1Y to 6Y GND VCC Pin description Pin 1, 3, 5, 9, 11, 13 2, 4, 6, 8, 10, 12 7 14 Description data input 1 data output 1 ground (0 V) supply voltage
74HC_HCT14
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 19 September 2012
4. Ordering information
Table 1. Ordering information Package Temperature range 74HC14N 74HCT14N 74HC14D 74HCT14D 74HC14DB 74HCT14DB 74HC14PW 74HCT14PW 74HC14BQ 74HCT14BQ 40 C to +125 C DHVQFN14 40 C to +125 C TSSOP14 40 C to +125 C SSOP14 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm plastic shrink small outline package; 14 leads; body width 5.3 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT108-1 SOT337-1 SOT402-1 40 C to +125 C Name DIP14 Description plastic dual in-line package; 14 leads (300 mil) Version SOT27-1 Type number
plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm
5. Functional diagram
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 19 September 2012
3 of 21
NXP Semiconductors
74HC14; 74HCT14
Hex inverting Schmitt trigger
2 of 21
NXP Semiconductors
74HC14; 74HCT14
Hex inverting Schmitt trigger
6. Pinning information
6.1 Pinning
terminal 1 index area 1Y 1A 1Y 2A 2Y 3A 3Y GND 1 2 3 4 5 6 7
7. Functional description
Table 3. Input nA L H
[1] H = HIGH voltage level; L = LOW voltage level.
Function table[1] Output nY H L
74HC_HCT14
All information provided in this document is subject to legal disclaimers.
74HC14; 74HCT14
Hex inverting Schmitt trigger
Rev. 6 — 19 September 2012 Product data sheet
1. General description
The 74HC14; 74HCT14 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74HC14; 74HCT14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
3. Applications
Wave and pulse shapers Astable multivibrators Monostable multivibrators
NXP Semiconductors
74HC14; 74HCT14
Hex inverting Schmitt trigger
Unit V mA mA mA mA mA C mW mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
(1) The die substrate is attached to this pad using conductive die attach material. It cannot be used as a supply pin or input.
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
2. Features and benefits
Low-power dissipation ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C
4 of 21
NXP Semiconductors
74HC14; 74HCT14
Hex inverting Schmitt trigger
10. Static characteristics
Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Tamb = 25 C Min 74HC14 VOH HIGH-level output voltage VI = VT+ or VT IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VT+ or VT IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC CI 74HCT14 VOH HIGH-level output voltage VI = VT+ or VT; VCC = 4.5 V IO = 20 A IO = 4.0 mA VOL LOW-level output voltage VI = VT+ or VT; VCC = 4.5 V IO = 20 A; IO = 4.0 mA; II ICC ICC input leakage current supply current additional supply current VI = VCC or GND; VCC = 5.5 V VI = VCC or GND; IO = 0 A; VCC = 5.5 V per input pin; VI = VCC 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V 0 0.15 30 0.1 0.26 0.1 2.0 108 0.1 0.33 1.0 20 135 0.1 0.4 1.0 40 147 V V A A A 4.4 3.98 4.5 4.32 4.4 3.84 4.4 3.7 V V input leakage current supply current input capacitance VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 0 0 0 0.15 0.16 3.5 0.1 0.1 0.1 0.26 0.26 0.1 2.0 0.1 0.1 0.1 0.33 0.33 1.0 20 0.1 0.1 0.1 0.4 0.4 1.0 40 V V V V V A A pF 1.9 4.4 5.9 3.98 5.48 2.0 4.5 6.0 4.32 5.81 1.9 4.4 5.9 3.84 5.34 1.9 4.4 5.9 3.7 5.2 V V V V V Typ Max Tamb = 40 C to +85 C Min Max Tamb = 40 C to +125 C Min Max Unit