• Separate Power for digital, analog and Crystal
Bead Digital Crystal
47uF 0.1uF back
Decouple Cap.
• Put decouple capacitors at every pair of P/G
• As near as possible
back
Power/Ground Lines
• Width of P/G Ring around core enough for average current of whole chip 1um 1mA
• P/G trunks space and width
back
Heat
• Bipolar Higher Temperature Higher Current “Thermal Run Away”.
• Clock Tr/Tf as small as possible to avoid jitter
back
Power/Ground
Regulator
• All ground connected
Power
• Ground-Sea as large asSupply possible
Analog1 Analog2
• CMOS Higher Temperature Lower Current Worse speed performance
• IC dice is hotter than package surface • 散熱片
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Clock
• Low speed Clock/Reset signal must have Schmidt-trigger as input buffer
Chip 47uF 0.1uF
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Clock Lines
• Clock: any signal triggering other circuit by edges
• Apart from other signals as far as possible • As short as possible • If a jump line is needed, use ground line to
高頻電路的設計及測試
江明澄
Index
• IC A Extracted Cap. A Power/Ground Pins A Power/Ground
Lines A Heat A Clock
• PCB A Power/Ground A Decouple Cap. A Clock Lines
• Q&A D
• Separate P/G for I/O, Core, and Crystal • Separate P/G for analog and digital • Dedicated P/G for high driving I/O • Put pins of every P/G pair together • As many as possible • Arranged around whole chip
Extracted Cap.
• Coupled Ca.
back
Miller Effect of Extracted Cap.
CLK 3.3V 0V
CLKB 0V 3.3V
Q=C*V=C*2*3.3=(2*C)*3.3
CLK CLKB back
Power/Ground Pins
shield.
back
Q&A
• Why Slot Rule? • Why Antenna Rule? • What is CMP? Why?
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