always@(negedgeclk or posedge reset)begin
if(reset == 1)
state <= st0;
end
always@(negedgeclk)begin
case(state)
st0: state <= date_in?st1:st0;
st1: state <= date_in?st2:st0;
st2: state <= date_in?st2:st3;
st3: state <= date_in?st1:st0;
// st4: state <= date_in?st2:st0;
endcase
end
assign date_out = (date_in& state[0] & state[1]);
endmodule
/***********测试程序*********/
`timescale 1ns/100ps
module selec_td1;
reg clk1,reset1,datein;
wire dateout;
mealy1101 u1(.clk(clk1),.reset(reset1),.date_in(datein),.date_out(dateout));
input reset,clk,date_in;
output date_out;
reg[2:0] state;
parameter st0 = 3'b000，st1 = 3'b001,st2 = 3'b010,st3 = 3'b011,st4 = 3'b100;
always@(negedgeclk or posedge reset)begin
reset1 = 0;
#5 reset1 = 1;
end
always fork
#10 clk1 = ~clk1;
#10 datein = $random;
join
Endmodule
/**********仿真波形***************/
Mealy型
/*********1101序列检测器代码*******/
initial begin
clk1 = 0;
reset1 = 0;
#5 reset1 = 1;
end
always fork
#10 clk1 = ~clk1;
#10 datein = $random;
join
endmodule
/**********仿真波形***************/
1101序列检测器实验报告
实验名称
1101序列检测器设计
实验时间实验地点实源自人姓名合作者学号
实验小组
第组
实验性质
□验证性□设计性□综合性□应用性
实验成绩：
评阅教师签名：
Moore型
/*********1101序列检测器代码*******/
module moore1101(reset ,clk ,date_in ,date_out);
module selec_td2;
reg clk1,reset1,datein;
wire dateout;
moore1101 u2(.clk(clk1),.reset(reset1),.date_in(datein),.date_out(dateout));
initial begin
clk1 = 0;
if(reset == 1)
state <= st0;
end
always@(negedgeclk)begin
case(state)
st0: state <= date_in?st1:st0;
st1: state <= date_in?st2:st0;
st2: state <= date_in?st2:st3;
module mealy1101(reset ,clk ,date_in ,date_out);
input reset,clk,date_in;
output date_out;
reg[1:0] state;
parameter st0 = 2'b00,st1 = 2'b01,st2 = 2'b10,st3 = 2'b11;
st3: state <= date_in?st4:st0;
st4: state <= date_in?st2:st0;
endcase
end
assign date_out = state[2];
endmodule
/***********测试程序*********/
`timescale 1ns/100ps