library ieee;
use ieee.std_logic_1164.all;
entity vgactr is
port( c lk:in std_logic;
rst:in std_logic;
red:out std_logic;
green:out std_logic;
blue:out std_logic;
H_Sync:out std_logic;
V_Sync:out std_logic);
end vgactr;
architecture behavioral of vgactr is
signal cnt_H:integer range 0 to 799;
signal cnt_V:integer range 0 to 520;
signal clk_H:std_logic:='0';
signal clk_V:std_logic:='0';
signal colorbuf:std_logic_vector(0 to 2);
begin
red<=colorbuf(0);
green<=colorbuf(1);
blue<=colorbuf(2);
--50MHz分频为25MHz，作为水平扫描信号的时钟process(clk)
variable n:integer range 0 to 1;
begin
if rising_edge(clk)then
clk_H<=not clk_H;
end if;
end process;
--水平扫描计数，并产生竖直扫描计数的时钟
process(clk_H,Rst)
begin
if rst='1' then
cnt_H<=0;
clk_V<='1';
elsif rising_edge(clk_H)then
if cnt_H=799 then
cnt_H<=cnt_H+1;
end if;
if cnt_H<=399 then
clk_V<='1';
else
clk_V<='0';
end if;
end if;
end process;
--竖直扫描计数
process(clk_V,rst)
begin
if rst='1' then
cnt_V<=0;
elsif rising_edge(clk_V)then
if cnt_V=520 then
cnt_V<=0;
else
cnt_V<=cnt_V+1;
end if;
end if;
end process;
--产生水平扫描信号和竖直扫描信号process(clk,rst)
begin
if rst='1' then
H_Sync<='0';
V_Sync<='0';
elsif rising_edge(clk) then
if cnt_H<=95 then
H_Sync<='0';
else
H_Sync<='1';
end if;
if cnt_V=1 then
V_Sync<='0';
else
V_Sync<='1';
end if;
end if;
end process;
--输出颜色控制
process(clk,rst)
begin
if rst='1' then
colorbuf<="000";
elsif rising_edge(clk) then
case cnt_H is
when 144 to 223 =>colorbuf<="000";
when 224 to 303 =>colorbuf<="001";
when 304 to 383 =>colorbuf<="010";
when 384 to 463 =>colorbuf<="011";
when 464 to 543 =>colorbuf<="100";
when 544 to 623 =>colorbuf<="101";
when 624 to 703 =>colorbuf<="110";
when 704 to 784 =>colorbuf<="111";
when others=>colorbuf<="000";
end case;
end if;
end process;
end;。