Cox
(fF/m2)
Co
(fF/m)
Cj
(fF/m2)
mj
b
(V)
Cjsw
(fF/m)
mjsw 0.44 0.32
bsw
(V)
NMOS PMOS
6 6
0.31 0.27
2 1.9
0.5 0.9 0.48 0.9
0.28 0.22
0.9 0.9
CSE477 L08 Capacitance.15
Irwin&Vijay, PSU, 2003
CSE477 L08 Capacitance.9
MOS Diffusion Capacitances

The junction (or diffusion) capacitance is from the reverse-biased source-body and drain-body pn-junctions.
CSE477 L08 Capacitance.16 Irwin&Vijay, PSU, 2003
Gate-Drain Capacitance: The Miller Effect

M1 and M2 are either in cut-off or in saturation. The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor).
Irwin&Vijay, PSU, 2003
CSE477 L08 Capacitance.12
Reverse-Bias Diode Junction Capacitance
2 1.5
abrupt (m=1/2)
Cj (fF)
1 0.5 0 -5 -4 -3 -2 -1 VD (V) 0 1
linear (m=1/3)
M2 pdrain
CG4 CDB2
M4
Vin
Vout
Cw CDB1 CG3
M3
Vout2
CGD12 ndrain
M1
intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance
90%
output waveform
50% 10%
signal slopes
tf
CSE477 L08 Capacitance.2
tr
t
Irwin&Vijay, PSU, 2003
CMOS Inverter: Dynamic

Transient, or dynamic, response determines the maximum speed at which a device can be operated.
MOS Channel Capacitances

The gate-to-channel capacitance depends upon the operating region and the terminal voltages CGD = CGCD + CGDO
D
CGS = CGCS + CGSO
G
VGS
S
-
+
D
n+
n+
n channel
p substrate
depletion region
CSB = CSdiff
B
CSE477 L08 Capacitance.10
CDB = CDdiff
Irwin&Vijay, PSU, 2003
Source Junction View
channel-stop implant (NA+) W source bottom plate (ND)
CSE477 L08 Capacitance.1
Irwin&Vijay, PSU, 2003
Review: Delay Definitions
Vin Vout
Vin
Propagation delay input waveform
50%
tp = (tpHL + tpLH)/2 t
tpHL Vout
tpLH
Irwin&Vijay, PSU, 2003
Review: Sources of Capacitance
Vin Vout CL CG4
M4
Vout2
M2VinCGFra bibliotek12pdrain
ndrain
CDB2 CDB1
Vout
Cw
M3
Vout2
M1
CG3
intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance
where Cj0 is the capacitance under zero-bias conditions (a function of physical parameters), 0 is the built-in potential (a function of physical parameters and temperature) and m is the grading coefficient
NMOS
VT0(V) 0.43
VDSAT(V) 0.63
k’(A/V2) 115 x 10-6
PMOS
CSE477 L08 Capacitance.8
-0.4
-0.4
-1
-30 x 10-6
-0.1
Irwin&Vijay, PSU, 2003
Average Distribution of Channel Capacitance
VGS
G
+
S
-
n+
n+
n channel
CGB = CGCB
p substrate
depletion region
B
CSE477 L08 Capacitance.7 Irwin&Vijay, PSU, 2003
Review: Summary of MOS Operating Regions

Cutoff (really subthreshold) VGS VT
Review: Reverse Bias Diode

All diodes in MOS digital circuits are reverse biased; the dynamic response of the diode + is determined by depletion-region charge or VD junction capacitance Cj = Cj0/((1 – VD)/0)m
ID = k’ W/L [(VGS – VT)VDS – VDS2/2] (1+VDS) (VDS)

Saturated (Constant Current) VDS VDSAT = VGS - VT
IDSat = k’ W/L [(VGS – VT)VDSAT – VDSAT2/2] (1+VDS) (VDS) (V0.5) 0.4 (V-1) 0.06
lateral diffusion Source n+ Poly Gate
Top view
xd
Ldrawn
xd
Drain W n+
n+
Leff
tox n+
Overlap capacitance (linear) CGSO = CGDO = Cox xd W = Co W
CSE477 L08 Capacitance.6 Irwin&Vijay, PSU, 2003

m = ½ for an abrupt junction (transition from n to p-material is instantaneous) m = 1/3 for a linear (or graded) junction (transition is gradual)

Nonlinear dependence (that decreases with increasing reverse bias)

Exponential in VGS with linear VDS dependence ID = IS e (qVGS/nkT) (1 - e -(qVDS/kT) ) (1 - VDS) where n 1

Strong Inversion VGS > VT

Linear (Resistive) VDS < VDSAT = VGS - VT
Operation Region CGCB CGCS CGCD CGC CG
Cutoff
Linear (Resistive) Saturation
CoxWL
0 0
0
CoxWL/2 (2/3)CoxWL
0
CoxWL/2 0
CoxWL
CoxWL
CoxWL + 2CoW
CoxWL + 2CoW
(2/3)CoxWL (2/3)CoxWL + 2CoW