FPGA实现步进电机控制源代码.txt我爸说过的最让我感动的一句话：“孩子，好好学习吧，爸以前玩麻将都玩儿10块的，现在为了供你念书，改玩儿1块的了。

”module fenpin(clk_48m,reset,out_door,addr,data,data_rd,rd,rw,Grating_a,Grating_b); input clk_48m,data_rd,reset,rd,rw,Grating_a,Grating_b;
input [8:0]addr;
output out_door;
inout [7:0]data;
reg flag;
reg [23:0]step;
reg [23:0]pul_counter;
reg [5:0]clk_div1m;
reg [23:0]den;
reg [23:0]counter;
reg [23:0]counter_now;
reg [19:0]Grating_counter;
reg [7:0]com;
reg [7:0]databuff;
reg out=0;
reg data_link;
reg direct;
assign data=data_link?databuff:8'bzzzzzzzz;
assign out_door=out&flag;
always@(posedge clk_48m)
if(clk_div1m<6'h2e)
clk_div1m <=clk_div1m+1;
else
clk_div1m<=0;
assign clk_1m=(clk_div1m==6'h2e);
always @(posedge clk_1m)
begin
if(!reset)
begin
counter_now<=24'b1111_1111_1111_1111_1111_1111; end
else if(com[0:0]==1'b1)
begin
if(counter_now>den)
begin
counter_now<=counter_now-1;
end
else
begin
end
end
else
begin
end
end
always @(posedge clk_48m)
begin
if(!reset)
begin
counter<=0;
end
else if(com[0:0]==1'b1)
begin
if(counter==counter_now-1)
begin
counter<=0;
out=~out;
end
else
begin
counter<=counter+1;
end
end
else
begin
end
end
always @ (posedge out)
begin
if(!reset)
begin
flag<=1;
pul_counter<=0;
end
else
begin
if(pul_counter==step)
begin
flag<=0;
pul_counter<=0;
end
else pul_counter<=pul_counter+1;
end
end
always@(posedge Grating_a)
if(Grating_b==1)
direct=1;
else direct=0;
always@(posedge Grating_a)
begin
if(!reset)
Grating_counter=0;
else if(direct==1)
Grating_counter<=Grating_counter+1;
else Grating_counter<=Grating_counter-1; end
always @(posedge clk_48m)
begin
if(!reset)
begin
data_link<=1'b0;
end
else if(rw)
begin
data_link<=1'b1;
end
end
always @( posedge clk_48m )
begin
if(!reset)
begin
step<=0;
den<=0;
com<=0;
end
else if(data_rd&rw&!rd)
case(addr)
3'b000 : den[7:0]<= data;
3'b001 : den[15:8]<= data;
3'b010 : den[23:16]<=data;
3'b011 : step[7:0]<= data;
3'b100 : step[15:8]<= data;
3'b101 : step[23:16]<=data;
3'b110 : com[7:0]<=data;//数据传送完毕
endcase
else
begin
end
end
always @(posedge clk_48m)
begin
if(!reset)
begin
databuff<=0;
end
else if(data_rd&rd&!rw)
case(addr)
8'h00:databuff<=den[7:0];
8'h01:databuff<=den[15:8];
8'h02:databuff<=den[23:16];
8'h03:databuff<=step[7:0];
8'h04:databuff<=step[15:8];
8'h05:databuff<=step[23:16];
8'h06:databuff<=com[7:0];
8'h07:databuff<=Grating_counter[7:0];
8'h08:databuff<=Grating_counter[15:8];
8'h09:databuff<={4'h0,Grating_counter[19:16]}; endcase
else
begin
end end endmodule。