状态机：LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY xhd ISPort(clk : in std_logic;ra,rb,ya,yb,ga,gb : out std_logic );END xhd;Architecture a of xhd istype state is (S0,S1,S2,S3);signal presentstate,nextstate : state;signal tmp1,tmp2 : integer range 0 to 30;signal timeout1,timeout2: std_logic;signal q: std_logic_vector(21 downto 0);signal sec: std_logic;Begin----get 1 hz clock pulseprocess(clk)beginif clk'event and clk='1' then q<=q+1; end if;sec<=q(21); --get 1 hz clock pulseend process;timing: process(sec)beginif sec'event and sec='1' thenif tmp1=29 then timeout1<='1'; timeout2<='0'; tmp1<=0; else if timeout1='1' thenif tmp2=4 then timeout2<='1'; timeout1<='0'; tmp2<=0;else tmp2<=tmp2+1; end if;else tmp1<=tmp1+1; end if;end if;end if;end process;changestate: process(presentstate)Begincase presentstate iswhen S0 => if timeout1='0' thennextstate<=s0;ra<='0'; ya<='0'; ga<='1';rb<='1'; yb<='0'; gb<='0';else nextstate<=s1; end if;when S1 => if timeout2='0' thennextstate<=s1;ra<='0'; ya<='1'; ga<='0';rb<='1'; yb<='0'; gb<='0';else nextstate<=s2; end if;when S2 => if timeout1='0' thennextstate<=s2;ra<='1'; ya<='0'; ga<='1';rb<='0'; yb<='0'; gb<='1';else nextstate<=s3; end if;when S3 => if timeout2='0' thennextstate<=s3;ra<='1'; ya<='0'; ga<='0';rb<='0'; yb<='1'; gb<='0';else nextstate<=s0; end if;when others => nextstate<=s0;timeout1<='0'; timeout2<='0';end case;end process;end a;ENTITY xhd ISPort(clk : in std_logic;ra,rb,ya,yb,ga,gb : out std_logic );END xhd;Architecture a of xhd is 里面的xhd根据你们文件具体情况设定秒表10进制--*******************************************--程序包library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;--*******************************************--实体ENTITY shijinzhi is--Cn 计数脉冲--Rest 清零信号-- En 允许计数信号--Dout[3..0] 十进制BCD码-- Cy 进位码port(Cn,Rest,En :in std_logic;Dout : out std_logic_VECTOR ( 3 Downto 0 );Cy : out std_logic);end shijinzhi ;--******************************************* --结构体architecture sun1 of shijinzhi isbeginProcess (Cn,Rest,En)Variable Cqi : std_logic_VECTOR ( 3 Downto 0 ); BeginIf Rest ='1' Then Cqi :=(Others =>'0');Cy<='0';Elsif Cn'Event and Cn='1' thenIf En='1' thenIf Cqi <"1001" thenCqi :=Cqi+1;Cy<='0';elsif cqi="1001"then Cy<='1';Cqi :=(others =>'0');end If;end If;end If;Dout<=Cqi;END Process;End sun1;--******************************************* 修改同上编写成功后，封装六进制：--******************************************* --程序包library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;--******************************************* --实体ENTITY liujinzhi is--CLK 计数脉冲--RST 清零信号-- EN 允许计数信号--Dout[3..0] 十进制BCD码-- CY 进位码port(CLK,RST,EN :in std_logic;DOUT : out std_logic_VECTOR ( 3 Downto 0 );CY : out std_logic);end liujinzhi ;--*******************************************--结构体architecture SUN2 of liujinzhi isbeginProcess (CLK,RST,EN)Variable Cq : std_logic_VECTOR ( 3 Downto 0 );BeginIf RST ='1' Then Cq :=(Others =>'0');CY<='0';Elsif CLK'Event and CLK='1' thenIf EN='1' thenIf Cq <"0101" thenCq :=Cq+1;CY<='0';elsif cq="0101"then CY<='1';Cq :=(others =>'0');end If;end If;end If;DOUT<=Cq;END Process;End SUN2;--*******************************************修改同上：编译、封装七段：程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY qiwei ISPORT ( Q : IN STD_LOGIC_VECTOR(3 DOWNTO 0);DOUT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END qiwei; ARCHITECTURE behave OF qiwei ISBEGINPROCESS(Q) BEGINCASE Q ISWHEN "0000"=> DOUT<="0111111";WHEN "0001"=> DOUT<="0000110";WHEN "0010"=> DOUT<="1011011";WHEN "0011"=> DOUT<="1001111";WHEN "0100"=> DOUT<="1100110";WHEN "0101"=> DOUT<="1101101";WHEN "0110"=> DOUT<="1111101";WHEN "0111"=> DOUT<="0000111";WHEN "1000"=> DOUT<="1111111";WHEN "1001"=> DOUT<="1101111";WHEN OTHERS=> DOUT<="0000000";END CASE;END PROCESS;END behave;修改同上，编译，封装仿真波形如图所示：分频（1）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fenpin isport ( CLK:in std_logic;FCLK:out std_logic);end fenpin;architecture bhv of fenpin issignal CK:std_logic;beginprocess(CLK)variable counter:integer range 0 to 100000;beginif(CLK'EVENT AND CLK='1') THENIF(counter=99999)THEN counter:=0;CK<=NOT CK;ELSE counter:=counter+1;end if;end if;end process;FCLK<=CK;end bhv;分频（2）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fenpin isport ( clk,clr:in std_logic;q:buffer std_logic);end fenpin;architecture b of fenpin issignal counter:integer range 0 to 49999;beginprocess(clr,clk)beginif(CLK='1' AND clk'EVENT) THENIF clr='1' then counter<=0;ELSIF COUNTER=49999 THEN counter<=0;q<=not q;ELSE counter<=counter+1;END IF;END IF;end process;end b;。