中北大学课程设计说明书学生姓名:甘世伟学号：04学院: 电子与计算机科学技术学院专业: 微电子学题目: 利用拨码开关控制液晶显示器进行ASIC字符显示指导教师：王红亮职称: 讲师2010 年 6 月 25 日目录表—1：OCMJ2X8（128X32）引脚说明....................- 12 -硬件接口 ..................................................................................................................................................................... - 13 -四、电性能参数 ......................................................................................................................................................... - 13 -1）表—1模块时间参数表.........................- 13 -2）表—2模块主要电气参数表.......................- 14 -用户命令 ..................................................................................................................................................................... - 14 -外型尺寸图（图11） .............................................................................................................................................. - 15 -6.附录：液晶显示器简介 (13)1、课程设计目的（1）学习操作数字电路设计实验开发系统，掌握液晶显示器的工作原理及应用。

（2）掌握组合逻辑电路、时序逻辑电路的设计方法。

（3）学习掌握可编程器件设计的全过程。

2、课程设计内容和要求：、设计内容用VHDL语言编写程序，利用拔码开头控制液晶显示器进行ASIC字符显示。

、设计要求（1）学习掌握拔码开头控制模块、液晶显示模块的工作原理及应用；（2）熟练掌握VHDL编程语言，编写键盘控制模块的控制逻辑；（3）仿真所编写的程序，模拟验证所编写的模块功能；（4）下载程序到芯片中，硬件验证所设置的功能，能够实现ASIC字符的显示；（5）整理设计内容，编写设计说明书.3、设计方案及实现情况、设计思路运用VHDL语言进行各个模块的程序编写,该设计共有四个模块分别为:拨码模块;消抖模块;译码模块;显示模块.整个、模块共有四个单元电路组成为：图1图1 原理图、工作原理及框图图2 系统电路原理图、各模块功能描述(1)拨码模块程序代码为:library ieee;use bm1 isport(rst:in std_logic;译码消抖液晶显示拨码控制xd: in std_logic;clk: in std_logic;xdout: out std_logic );end bm1;architecture a of bm1 issignal count:integer range 0 to 100; beginprocess(clk,rst,xd)beginif(rst='0')thencount<=0;xdout<='0';elsif(clk'event and clk='1')thenif(count=5)thencount<=0;xdout<=not xd;elsecount<=count+1;end if;end if;end process;end a;(2)消抖模块程序代码为:Library ieee;use xd isport(aj:in std_logic;rst:in std_logic;ajout:out std_logic_vector(4 downto 0)end xd;architecture ajwork of xd issignal q: std_logic;signal count : std_logic_vector(4 downto 0); beginq<=aj when rst='1'else '0';process(q,rst)beginif(rst='0')thencount<="00000";elsif q'event and q='1' thenif count="11111" thencount<="00000";elsecount<=count+1;end if;end if;ajout<=count;end process;end ajwork;(3)译码模块程序代码为:library ieee;use ym1 isport(ym:in std_logic_vector(4 downto 0);Y:out std_logic_vector(7 downto 0));end ym1;architecture yima_arch of ym1 issignal a:std_logic_vector(4 downto 0);beginY<="01000001" when ( a="00000" ) else "01000010" when ( a="00001" ) else "01000011" when ( a="00010" ) else "01000100" when ( a="00011" ) else "01000101" when ( a="00100" ) else "00100001" when ( a="00101" ) else "00100011" when ( a="00110" ) else "00100100" when ( a="00111" ) else "00100101" when ( a="01000" ) else "00100110" when ( a="01001" ) else "00100111" when ( a="01010" ) else "00101000" when ( a="01011" ) else "00101001" when ( a="01100" ) else "00101010" when ( a="01101" ) else "00101011" when ( a="01110" ) else "00101100" when ( a="01111" ) else "00101101" when ( a="10000" ) else "00101110" when ( a="10001" ) else "00101111" when ( a="10010" ) else "00110000" when ( a="10011" ) else "00110001" when ( a="10100" ) else "00110010" when ( a="10101" ) else "00110011" when ( a="10110" ) else "00110100" when ( a="10111" ) else "00110101" when ( a="11000" ) else "00110110" when ( a="11001" ) else "00110111" when ( a="11010" ) else "00111000" when ( a="11011" ) else "00111001" when ( a="11100" ) else"00111010" when ( a="11101" ) else"00111011" when ( a="11110" ) else"00111100" when ( a="11111" ) else"00110000";end yima_arch;(4)显示模块程序代码为:LIBRARY IEEE;USE lcd ISPORT( busy :IN STD_LOGIC;clk_fsm :IN STD_LOGIC;db_ascii :IN STD_LOGIC_VECTOR(7 DOWNTO 0);req :OUT STD_LOGIC;db :OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END lcd;ARCHITECTURE rtl OF lcd ISSIGNAL ready : STD_LOGIC;TYPE state IS (CMD_SEND,XX_SEND,YY_SEND,ASCII_SEND); SIGNAL current_state : state;--SIGNAL db_send: std_logic_vector(7 downto 0);BEGINPROCESS(clk_fsm,busy,ready,db_ascii)variable cnt1: std_logic_vector(2 downto 0);BEGIN--db_send<=db_ascii;IF rising_edge(clk_fsm) THENCASE current_state ISWHEN CMD_SEND =>IF busy='0' THENIF ready='1' THENcurrent_state <= XX_SEND;ready <= '0';ELSEdb <= "";--F1req <= '1';ready <= '0';END IF;ELSEreq <= '0';ready <= '1';current_state <= CMD_SEND;END IF;WHEN XX_SEND =>IF busy='0' THENIF ready='1' THENcurrent_state <= YY_SEND;ready <= '0';ELSEdb <= "00001001";--07req <= '1';ready <= '0';END IF;ELSEreq <= '0';ready <= '1';current_state <= XX_SEND;END IF;WHEN YY_SEND =>IF busy='0' THENIF ready='1' THENcurrent_state <= ASCII_SEND;ready <= '0';ELSEdb <= "00000010";--02req <= '1';ready <= '0';END IF;ELSEreq <= '0';ready <='1';current_state <= YY_SEND;END IF;WHEN ASCII_SEND =>IF busy='0' THENIF ready='1' THENcurrent_state <= CMD_SEND;ready <= '0';ELSEdb <=db_ascii;req <= '1';ready <= '0';END IF;ELSEreq <= '0';ready <= '1';current_state <= ASCII_SEND;END IF;END CASE;END IF;END PROCESS;END rtl;、仿真结果（1）液晶显示器仿真结果: 当BUSY信号有效时（BUSY=‘1’），停止输出地址信号；当液晶模块处于空闲状态（BUSY=‘0’）时，输出地址信号。