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MDR/MAR act as interface between CPU and memory
The relationship between the MDR, the MAR, and memory
Address
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Copyright 2013 John Wiley & Sons, Inc.
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ALU (arithmetic logic unit) CU (control unit)
◦ Performs calculations and comparisons


MAR hold the address in the memory that is to be opened for data. Each bit has an address line.


CPU copies an address to MAR-Same time CPU sends message to memory unit whether it is a read/write CPU turns on switch that connects MDR with MAR by using activation line. Address decoder interprets address and activates address line in memory Switch activated between memory and MDR and transfer takes place
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•Single, permanent storage location within the CPU used for a particular defined purpose. •Each register in the CPU performs a specific role •Unlike memory in which every address is like any other address, each register serves a specific purpose. •Register size, the way its wired reflect its special function •Register maybe as small as a single bit or as wide as several bytes-range 1-128 bits
◦ Subcomponents: Memory management unit: supervises fetching
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Every instruction executed by the CPU requires memory access Primary memory holds program instructions and data Secondary storage is used for long term storage
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Use of Registers
◦ Scratchpad for currently executing program
◦ Stores information about status of CPU and currently executing program
◦ Performs fetch/execute cycle
Accesses program instructions and issues commands to the ALU Moves data to and from CPU registers and other hardware components instructions and data from memory I/O Interface: sometimes combined with memory management unit as Bus Interface Unit
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Copyright 2013 John Wiley & Sons, Inc.
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Address Line is turned on only if the computer is addressing the data within the cell The read/write determines whether the data will be transferred from the the cell to the MDR or from the MDR to the cell. R switch if on connects output of the cell to MDR line. W switch if on connect input of the cell to MDR which transfers the data bit on the MDR line to the cell for storage Activation Line




Each memory location has a unique address Address from an instruction is copied to the MAR which finds the location in memory MAR and MDR act as an Interface bween CPU and Memory. CPU determines if it is a store or retrieval Transfer takes place between the MDR and memory MDR is a two way register
◦ Data is moved from secondary storage to primary memory for CPU execution
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Small, permanent storage locations within the CPU used for a particular purpose Manipulated directly by the Control Unit Wired for specific function Size in bits or bytes (not in MB like memory) Can hold data, an address, or an instruction How many registers does the LMC have? What are the registers in the LMC?



Reg can be loaded with values from er location Data from another location can be added or subtracted from value previously stored in the register, leaving the sum or difference Data in the register can be shifted.
◦ Status of CPU and currently executing program ◦ Flags (one bit Boolean variable) to track condition like arithmetic carry and overflow, power failure, internal computer error
Hold intermediate results or data values, e.g., loop counters Equivalent to LMC’s calculator Typically several dozen in current CPUs
Chapter 7 CPU and Memory
Data
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Copyright 2013 John Wiley & Sons, Inc.
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7.3
Memory Unit Operation of Memory
Each cell in memory unit holds i bit of data.. In diagram above, each cellis organized in rows, Each row consists of one or more bytes. MAR holds address in memory that needs to be opened or activared In the diagram, what does 2n-1 represents? There is a separate address line for each row of cells in the memory, If there are n bits of addressing, there will be 2n address lines