数字起航—数控分频器零基础电子设计系列课程主讲人：范秋华国家级电工电子实验教学中心（青岛大学）4.4.5 数控分频器定义实现分频值与计数初值、计数器模的关系举例数控分频器数控分频器就是当在输入端给定不同输入数据时,将对输入的时钟信号clk进行相应的分频输出clkout。

10.Architecture a of fdiv is11.signal cnt: integer range 0 to n;12.signal temp: std_logic;13.Begin14.process (clk)15.begin16.if (clk'event and clk='1') then17.if(cnt<n ) then cnt<= cnt+1; temp <= ‘0’;18.else cnt<= 0; temp=‘1’;19.end if; end if;20.end process;21.clkout<= temp;22.End a;case keys7 iswhen "0000001" => if (clk'event and clk='1') thenif count <"11111111111111110" then count:=count + 1; fullspks<= '0'; else fullspks<='1'; count:=0; end if;end if; --1when "0000010" => if (clk'event and clk='1') thenif count <"11111111111111100" then count:=count + 1;fullspks <= '0'; else fullspks<='1'; count:=0; end if;end if; --2when "0000100" => if (clk'event and clk='1') thenif count <"11111111111111000" then count:=count + 1;fullspks <= '0'; else fullspks<='1'; count:=0; end if;end if; --3when "0001000" => if (clk'event and clk='1') thenif count <"1111111111110000" then count:=count + 1;fullspks <= '0'; else fullspks<='1'; count:=0; end if;end if; --4when "0010000" =>if (clk'event and clk='1') thenif count <"1111111111110000" then count:=count + 1; fullspks<= '0'; else fullspks<='1'; count:=0; end if;end if; --5when "0100000" =>if (clk'event and clk='1') thenif count <"1111111111100000" then count:=count + 1; fullspks<= '0'; else fullspks<='1'; count:=0; end if;end if; --6when others => null;end case;end process;process (keys7,clk)Variable count: integer range 0 to 20;beginif (clk'event and clk='1') thencase keys7 iswhen "0000001" => if count <4 then count:=count + 1; fullspks<= '0'; else fullspks<='1'; count:=0;end if; --1when "0000010" => if count <6 then count:=count + 1;fullspks <= '0'; else fullspks<='1'; count:=0;end if; --2when "0000100" => if count <8 then count:=count + 1;fullspks <= '0'; else fullspks<='1'; count:=0;end if; --3when "0001000" => if count <10 then count:=count + 1;fullspks <= '0'; else fullspks<='1'; count:=0;end if; --4when "0010000" =>if count <12 then count:=count + 1; fullspks<= '0'; else fullspks<='1'; count:=0;end if; --5when "0100000" =>if count <14 then count:=count + 1; fullspks<= '0'; else fullspks<='1'; count:=0;end if; --6when others => null;end case; end if;End process；国家级电工电子实验教学中心数字启航数控分频器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shufen isport ( clk : in std_logic ; --时钟Tone : in std_logic_vector (12 downto 0 ); clkout : out std_logic);end shufen;architecture Behavior of shufen issignal fullspks : std_logic ;begin p1: process ( clk ,Tone)variable count12 : std_logic_vector( 12 downto 0 ) ;beginif (clk 'event and clk='1') thenif count12 <"1111111111111" thencount12:=count12 + 1; fullspks <= '0'; else fullspks <='1'; count12 := Tone;end if;end if;end process;Clkout<=fullspks;end ；p1: process ( clk,Tone)variable count10 : integer ( 99 downto0 ) ; beginif (clk'event and clk='1') thenif count10 < 99 thencount10:=count10 + 1; fullspks<= '0';else fullspks<='1'; count10 := Tone;end if;end if;end process;Clkout<=fullspks;end；注意分频值与计数初值、计数器模的关系计数器模：100分频值：10计数初值：90p1: process ( clk,Tone)variable count10 : std_logic_vector( 9downto0 ) ; beginif (clk'event and clk='1') thenif count10 <"1111111111" thencount10:=count10 + 1; fullspks<= '0';else fullspks<='1'; count10 := Tone;end if;end if;end process;Clkout<=fullspks;end；再见！。