Cache
Terminology
Latency & Bandwidth
The time requested for the cache miss depends on both the latency and bandwidth
. Latency determines the time to retrieve the first word of the block
memory and disk
Cache
Terminology
Cache hit when the CPU finds a requested data item in the cache
Cache miss When the CPU does not find a data item it needs in cache
A safe place for hiding or storing things The first level of the memory hierarchy encountered once the address leaves
the CPU Whenever buffering is employed to reuse commonly occurring items The cache and main memory have the same relationship as the main
. Bandwidth determines the time to retrieve the rest of the block
Cache
Terminology
Block A fixed-size collection of data containing the requested word Block is retrieved from the main memory and placed into the cache for reuse later
Pages Fixed-size blocks At anytime each pages resides either in main memory or on disk
Cache
Terminology
Page fault When the CPU references an item within a page that is not present in the cache or main memory. When page fault happens, CPU will switch to some other task while disk access occurs.
Computer Architecture 计算机系统结构
Chapter 4 Memory Hierarchy
Ideally one would desire an indefinitely large memory capacity such that any particular …word would be immediately available …We are …forced to recognize the possibility of constructing a hierarchy of memories each of which has greater capacity than the preceding but which is less quickly accessible.
Because of locality and the higher speed of smaller memories, a memory hierarchy can improve performance.
ቤተ መጻሕፍቲ ባይዱ
Memory Hierarchy
Level
1
Name
Registers
Typical size
A.W. Burks, ……
Memory Hierarchy
Registers Stack Cache
Memory Disk Other Storages
Memory Hierarchy
We focus on the memory hierarchy for desktop Registers Cache Main Memory Disk storage
80 - 250 1000 - 5000 operating system disk
5,000,000 20 - 150 operating system/operator CD or Tape
Small >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> large Fast <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< Slow
Registers and Stack
Built in CPU
(Top of Stack) TOS1
TOS2
processor register
ALU
Example: The code sequence for C=A+B:
Push A Push B Add Pop C
processor register 235
<1 KB
Implementation Technology
custom memory with multiple ports CMOS
Access time (ns)
0.25 - 0.5
Bandwidth (MB/sec) 20,000- 100,000
Managed by
compiler
Backed by
23
ALU
A B C
memory
A2
B3
C
5
memory
A=2 B=3 C=A+B=2+3=5
Push A : TOP1=2
Push B: TOP1=3 TOP2=2
Add: TOP1=5
POP C: move the data in TOP1 to memory C
Cache
First Memory After CPU
cache
2 Cache <16 MB on-chip or offchip CMOS SRAM 0.5 - 25 5000 - 10,000
hardware
main memory
3 Main memory <16 GB
4 disk storage >100 GB
CMOS DRAM magnetic disk