Secondary
– Units in the same library may use a common name – VHDL • Architectures • Package bodies – No Verilog secondary units

VHDL Predefined Libraries
Where
– – – – _primary.dat - encoded form of Verilog module or VHDL entity _primary.vhd - VHDL entity representation of Verilog ports <arch_name>.dat - encoded form of VHDL architecture verilog.asm and <arch_name>.asm - executable code files

ModelSim Design Units
Primary
– Must have a unique name in a given library – VHDL • Entities • Package Declarations • Configurations – Verilog • Modules • User Defined Primitives
Model Technology’s ModelSim
Main Window: Source Window:
Structure Window Wave & List Windows:
Process Window:
Signals & Variables Windows: Dataflow Window:
ModelSim/PLUS
– Designer can simulate mixed Verilog & VHDL at once
ModelSim/SE
– Premier version – All the features of PLUS along with additional features

ModelSim Libraries
Directories that contain compiled design units
– Both VHDL and Verilog are compiled into libraries
Two Types
– Working (default work) • Contains the current design unit being compiled • Must create a working library before compiling • Only one allowed per compilation – Resource • Contains designs units that can be referenced by the current compilation • Multiple allowed during compilation • VHDL libraries can be referenced by LIBRARY and USE clauses
VHDL
– Library std contains packages standard and textio • These packages should not be modified novice users
IEEEpure
– Contains only IEEE approved std_logic_1164 packages – Accelerated for simulation
IEEE
– Contains precompiled Synopsys and IEEE arithmetic packages – For std_logic base type – Accelerated for simulation

vlib <library_name> Command
Needed for libraries not located in the working directory Use vmap command

2
Map Logical Library Name(s)
Basic Simulation Steps
1 2 3 Create library(s) Map library to physical directory Compile source code - All HDL Code must be compiled - Different for Verilog and VHDL Start simulator Advance simulator
Analyzing Designs Using Model Technology’s ModelSim
Modelsim使用教程
1
Typical PLD Design Flow
2
Typical PLD Flow
Design Specification Design Entry RTL Simulation Design Synthesis Place & Route Gate Level Simulation Timing Analysis In-System Verification System Production
Synthesis
– Translate design into target technology primitives – Optimization • Meet required area and performance constraints
Place & Route
– Map the design to specific locations inside target technology – Specify which routing resources should be used
Easy-to-use Interface
– Common across platforms

Simulation with ModelSim
10
Agenda
Basic Simulation Steps User Interface Functional Simulation Quartus Output Simulation Files Timing Simulation

ModelSim OEM Features
Complete Standards Support
– – – – – – ‘87 VHDL ‘93 VHDL IEEE 1364-’95 Verilog SDF 1.0 - 3.0 VITAL 2.2b VITAL ‘95
Timing Analysis Verify performance specifications were met
– May require design edits
Board Design
– Simulate board design – Program and test device on board
-> vlib lpm_sim

Mapping Logical Library Names
Must map a Logical Library Name to Library Path (location)
– Files in library path must already have been compiled – Relative, absolute, and soft path names supported

Creating Libraries (UI)
Select a new library only and type library name
This command creates a library subdirectory in the local directory
Hale Waihona Puke 4 51Creating ModelSim library(s)
UI) From within Main Window: Design -> Create a New Library Cmd) From within Main, transcript window: ModelSim> vlib <library name>
– OEM Version allows for Verilog simulation OR VHDL simulation
ModelSim Products
ModelSim/VHDL or ModelSim/Verilog
– OEM
ModelSim/LNL
– Licenses Verilog or VHDL but not at the same time
Creates libraries Default is work
<library_name> _info any_verilog_module _primary.dat _primary.vhd verilog.asm any_vhdl_unit _primary.dat <arch_name>.dat <arch_name>.asm _lock
– Can accept menu input and command line input – Main discussion of class
Batch Mode
– Run batch files from DOS or UNIX prompt – Not discussed