一、实验课题实验要求：按照题目要求用硬布线（组合逻辑）控制法设计一个简单模型机的控制单元CU（微操作信号产生电路），决定外部的端口（名称、有效电平）和内部各元件的连接，画出系统框图和逻辑图，设计仿真数据，用VHDL编程和仿真。

主要元件设计：1．指令译码器功能要求：3-8译码器。

2．控制单元功能要求：假设该模型机有8条不同类型的指令。

包括：算术运算、逻辑运算、移位、数据传送、访存操作、转移等。

根据每条指令的功能和时序，分析其执行过程中需要在各个阶段产生的全部微操作，导出产生这些微操作控制信号的逻辑。

3．用层次结构设计的方法设计一个控制单元CU（微操作控制信号产生电路）。

包括指令译码器和控制单元。

功能要求：能够正确产生8条不同指令在执行过程中（每个机器周期、每拍）发出的全部微操作。

二、逻辑设计写该实验的逻辑设计，包括：顶层系统框图，下层各主要元件的系统框图。

顶层和下层各主要元件的端口（引脚）描述：端口名称、功能、有效电平、位数等。

逻辑图，必须在图中清楚地标出每个内部连接线的Signal（与VHDL 程序中的Signal一致）。

根据所用的描述方式，可能还需要有：真值表/功能表/逻辑函数等。

1、3-8译码器：系统框图：S是工作信号，当S=1时，3-8译码器工作；当S=0时，3-8译码器不工作。

A是输入信号，Y是输出信号S A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y01 0 0 0 0 0 0 0 0 0 0 1 加法1 0 0 1 0 0 0 0 0 0 1 0 与1 0 1 0 0 0 0 0 0 1 0 0 或1 0 1 1 0 0 0 0 1 0 0 0 左移1 1 0 0 0 0 0 1 0 0 0 0 右移1 1 0 1 0 0 1 0 0 0 0 0 数据传送1 1 1 0 0 1 0 0 0 0 0 0 取数1 1 1 1 1 0 0 0 0 0 0 0 无条件转移0 ×××0 0 0 0 0 0 0 0Y(0)<=S and (not A(2)) and (not A(1)) and (not A(0));Y(1)<=S and (not A(2)) and (not A(1)) and A(0);Y(2)<=S and (not A(2)) and A(1) and (not A(0));Y(4)<=S and A(2) and (not A(1)) and (not A(0)); Y(5)<=S and A(2) and (not A(1)) and A(0); Y(6)<=S and A(2) and A(1) and (not A(0)); Y(7)<=S and A(2) and A(1) and A(0); 2、控制单元：设计过程：把每条指令的实现分成取指令、分析指令、执行指令三个步骤，每一步由一个机器周期实现，一条指令的实现需要三个机器周期，即M1（取指周期）、M2（分析周期）、M3（执行周期）；每个机器周期由三个节拍组成，即T0、T1、T2。

如下图所示：1、加法指令：寄存器R1中的一个数与寄存器R0中的一个数相加，结果放在R1中。

即实现（R0）+（R1）→R12、与指令：寄存器R1中的一个数与寄存器R0中的一个数，结果放在R1中。

即实现（R1）and (R0) → R13、或指令：寄存器R1中的一个数或寄存器R0中的一个数，结果放在R1中。

即实现（R1）or (R0) → R14、逻辑左移指令：寄存器R1中的数左移，移动位数存放在寄存器R0中，结果放在R1中。

即实现（R1））左移（0R R15、逻辑右移指令：寄存器R1中的数左移，移动位数存放在寄存器R0中，结果放在R1中。

即实现（R1））右移（0R R16、数据传送指令：寄存器R0中的数据送到寄存器R1中。

即实现（R0）→ R1。

7、取数指令：取出存储器中的一个数（地址在寄存器R0中）送到寄存器R1中。

即实现 （（R0））→（R1）8、无条件转移指令：寄存器R1中的地址送到PC 中。

即实现（R1）→ PC8条指令的微操作如下表所示，以教材P122的CPU 控制图（省去了M/IO 、ADS ）为例： 由于每条指令取指周期的微操作是一样的，所以可以先设计取指周期微操作的节拍安排。

取指周期：T0：PC →AB ，W/R =0T1：DB →IR机器周期节拍T 0 T 1 T 2系统框图：PC→AB = M0·T0W/R=0 = M0·T0+M1·T1·取数DB→IR = M0·T1PC+1 = M0 ·T2rs1→GR = M1 ·T0(rs1)→ALU = M1 ·T0+ = M1 ·T0·取数+M2·T1·(加+传送+取数+转移)ALU→AR =M1 ·T1 ·取数AR→AB =M1·T1 ·取数rd→GR =M1 ·T2·(加法+与+或+左移+右移)(rd)→ALU = M1 ·T2·(加法+与+或+左移+右移)DB→DR = M1 ·T2·取数DR→ALU = M2 ·T0·取数∧= M2·T1·与∨= M2·T1·或←= M2·T1·左移→=M2·T1·右移ALU→GR = M2·T2·(加法+与+或+左移+右移+数据传送+取数) ALU→PC = M2·T2·转移3、层次结构控制单元：逻辑图：三、VHDL程序--3-8译码器library ieee;use ieee.std_logic_1164.all;entity decoder38 isport( S:in std_logic;A:in std_logic_vector(2 downto 0);Y:out std_logic_vector(7 downto 0)); end decoder38;architecture behave of decoder38 isbeginprocess(S)beginif S='1' thenY(0)<=(not A(2)) and (not A(1)) and (not A(0));Y(1)<=(not A(2)) and (not A(1)) and A(0);Y(2)<=(not A(2)) and A(1) and (not A(0));Y(3)<=(not A(2)) and A(1) and A(0);Y(4)<=A(2) and (not A(1)) and (not A(0));Y(5)<=A(2) and (not A(1)) and A(0);Y(6)<=A(2) and A(1) and (not A(0));Y(7)<=A(2) and A(1) and A(0);else Y<="00000000";end if;end process;--控制单元--3-8译码器library ieee;use ieee.std_logic_1164.all;entity CU isport( m:in std_logic_vector(2 downto 0);t:in std_logic_vector(2 downto 0);d:in std_logic_vector(7 downto 0);q:out std_logic_vector(18 downto 0));end CU;architecture behave of CU issignal iq:std_logic_vector(7 downto 0);beginiq(0)<=not d(7) and not d(6) and not d(5) and not d(4) and not d(3) and not d(2) and not d(1) and d(0);iq(1)<=not d(7) and not d(6) and not d(5) and not d(4) and not d(3) and not d(2) and d(1) and not d(0);iq(2)<=not d(7) and not d(6) and not d(5) and not d(4) and not d(3) and d(2) and not d(1) and not d(0);iq(3)<=not d(7) and not d(6) and not d(5) and not d(4) and d(3) and not d(2) and not d(1) and not d(0);iq(4)<=not d(7) and not d(6) and not d(5) and d(4) and not d(3) and not d(2) and not d(1) and not d(0);iq(5)<=not d(7) and not d(6) and d(5) and not d(4) and not d(3) and not d(2) and not d(1) and not d(0);iq(6)<=not d(7) and d(6) and not d(5) and not d(4) and not d(3) and not d(2) and not d(1) and not d(0);iq(7)<=d(7) and not d(6) and not d(5) and not d(4) and not d(3) and not d(2) and not d(1) and not d(0);q(0)<=not m(2) and not m(1) and m(0) and not t(2) and not t(1) and t(0);q(1)<=(not m(2) and not m(1) and m(0) and not t(2) and not t(1) and t(0))or (not m(2) and m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(6));q(2)<=not m(2) and not m(1) and m(0) and not t(2) and t(1) and not t(0);q(3)<=not m(2) and not m(1) and m(0) and t(2) and not t(1) and not t(0);q(4)<=not m(2) and m(1) and not m(0) and not t(2) and not t(1) and t(0);q(5)<=not m(2) and m(1) and not m(0) and not t(2) and not t(1) and t(0);q(6)<=(not m(2) and m(1) and not m(0) and not t(2) and not t(1) and t(0) and iq(6)) or(m(2) and not m(1) and not m(0) and not t(2) and t(1) and not t(0) and (iq(0) or iq(5) or iq(6) or iq(7)));q(7)<=not m(2) and m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(6);q(8)<=not m(2) and m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(6);q(9)<=not m(2) and m(1) and not m(0) and t(2) and not t(1) and not t(0) and(iq(0) or iq(1) or iq(2) or iq(3) or iq(4));q(10)<=not m(2) and m(1) and not m(0) and t(2) and not t(1) and not t(0) and(iq(0) or iq(1) or iq(2) or iq(3) or iq(4));q(11)<=not m(2) and m(1) and not m(0) and t(2) and not t(1) and not t(0) and iq(6);q(12)<=m(2) and not m(1) and not m(0) and not t(2) and not t(1) and t(0) and iq(6);q(13)<=m(2) and not m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(1);q(14)<=m(2) and not m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(2);q(15)<=m(2) and not m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(3);q(16)<=m(2) and not m(1) and not m(0) and not t(2) and t(1) and not t(0) and iq(4);q(17)<=m(2) and not m(1) and not m(0) and t(2) and not t(1) and not t(0)and (iq(0) or iq(1) or iq(2) or iq(3) or iq(4) or iq(5) or iq(6));q(18)<=m(2) and not m(1) and not m(0) and t(2) and not t(1) and not t(0) and iq(7);--层次结构控制单元library ieee;use ieee.std_logic_1164.all;entity HCU isport( S:in std_logic;A:in std_logic_vector(2 downto 0);M:in std_logic_vector(2 downto 0);T:in std_logic_vector(2 downto 0);Q:out std_logic_vector(18 downto 0)); end HCU;architecture struct of HCU issignal i:std_logic_vector(7 downto 0);ponent decoder38port( S:in std_logic;A:in std_logic_vector(2 downto 0);Y:out std_logic_vector(7 downto 0)); end ponent;ponent CUport( m:in std_logic_vector(2 downto 0);t:in std_logic_vector(2 downto 0);d:in std_logic_vector(7 downto 0);q:out std_logic_vector(18 downto 0)); end ponent;beginG1:decoder38 port map(S=>S,A=>A,Y=>i);G2:CU port map(d=>i,t=>T,m=>M,q=>Q);end struct;四、仿真设计3-8译码器仿真设计：设计数据，输出3-8译码器的译码后的8种编码。