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STM8 SWIM通信协议和调试模块中文手册翻译版

翻译:

本人应朋友之邀,翻译了本文的第三章,由于水平有限,且没有用过STM8系列的控制器,如有错误,请见谅。

by踏雪无痕

2010-11-11

rose_yiyong@http://biz.doczj.com/doc/9416432417.html,

December 2009Doc ID 14024 Rev 21/37

UM0470User manual

STM8 SWIM communication protocol and debug module Introduction

This manual has been written for developers who need to build programming, testing or debugging tools for the STM8 microcontroller family. It explains the debug architecture of the STM8 core.

The STM8 debug system consists of two modules:

●DM: Debug module ●

SWIM: Single wire interface module

Related documentation:●

STM8S Flash programming reference manual (PM0051)

STM8L Flash programming manual (PM0054)

http://biz.doczj.com/doc/9416432417.html,

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Contents UM0470

Contents

1Debug system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2Communication layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2SWIM entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3Bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3.1High speed bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3.2Low speed bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4SWIM communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5SWIM commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5.1SRST: system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5.2ROTF: read on the fly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5.3WOTF: write on the fly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6SWIM communication reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.7CPU register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.8SWIM communication in Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.9Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.10STM8 SWIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.10.1SWIM control status register (SWIM_CSR) . . . . . . . . . . . . . . . . . . . . . . 18

3.10.2SWIM clock control register (CLK_SWIMCCR) . . . . . . . . . . . . . . . . . . . 19

4Debug module (DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.1Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.2Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.3Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.4Watchdog control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.5Interaction with SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4Breakpoint decoding table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2/37Doc ID 14024 Rev 2

UM0470Contents

4.5Software breakpoint mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.6Timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.7Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.8Data breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.9Instruction breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.10Step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.11Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.11.1Illegal Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.11.2Forbidden stack access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.11.3DM break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.12DM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.12.1DM breakpoint register 1 extended byte (DM_BKR1E) . . . . . . . . . . . . . 27

4.12.2DM breakpoint register 1 high byte (DM_BKR1H) . . . . . . . . . . . . . . . . . 27

4.12.3DM breakpoint register 1 low byte (DM_BKR1L) . . . . . . . . . . . . . . . . . . 27

4.12.4DM breakpoint register 2 extended byte (DM_BKR2E) . . . . . . . . . . . . . 28

4.12.5DM breakpoint register 2 high byte (DM_BKR2H) . . . . . . . . . . . . . . . . . 28

4.12.6DM breakpoint register 2 low byte (DM_BKR2L) . . . . . . . . . . . . . . . . . . 28

4.12.7DM control register 1 (DM_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.12.8DM control register 2 (DM_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.12.9DM control/status register 1 (DM_CSR1) . . . . . . . . . . . . . . . . . . . . . . . 31

4.12.10DM control/status register 2 (DM_CSR2) . . . . . . . . . . . . . . . . . . . . . . . 32

4.12.11DM enable function register (DM_ENFCTR) . . . . . . . . . . . . . . . . . . . . . 33

4.12.12Summary of SWIM, DM and core register maps . . . . . . . . . . . . . . . . . . 34 Appendix A Description of the DM_ENFCTR register

for each STM8 product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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List of tables UM0470 List of tables

Table 1.SWIM command summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2.CPU register memory mapping in STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.SWIM pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4.Decoding table for breakpoint interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 5.STM8 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6.Peripherals which are frozen by the bits of the DM_ENFCTR register

for each STM8 product. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 7.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4/37Doc ID 14024 Rev 2

UM0470List of figures List of figures

Figure 1.Debug system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2.SWIM pin external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.SWIM activation sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4.SWIM activation timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5.SWIM entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6.High speed bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 7.Low speed bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure http://biz.doczj.com/doc/9416432417.html,mand format (Host -> Target) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 9.Data format (Target -> Host). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 10.Timings on SWIM pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11.Debug module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12.STM8 Instruction Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 13.STM8 Debug Module Stall Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14.STM8 DM Data Break Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 15.STM8 DM instruction break timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 16.STM8 DM step timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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Debug system overview UM0470

6/37Doc ID 14024 Rev 2

1

Debug system overview The STM8 debug system interface allows a debugging or programming tool to be connected to the MCU through a single wire bidirectional communication based on open-drain line.It provides non-intrusive read/write access to RAM and peripherals during program execution

The block diagram is shown in Figure 1.Figure 1.

Debug system block diagram

The debug module uses the two internal clock sources present in the device, the LSI Low Speed Internal clock (usually in the range 30 kHz-200 kHz, depending on the product) one and the HSI High Speed Internal clock (usually in the range 10 MHz to 25 MHz, depending on the device). The clocks are automatically started when necessary.

SWIM Entry

LSI oscillator HSI oscillator

Comm Layer Command Decode

Debug module (DM)STM8Core

Peripherals SWIM pin

P e r i p h e r a l B u s

CPU Bus

SWIM RAM

Flash/R A M B u s

STM8

Data EEPROM

?

UM0470Communication layer

Doc ID 14024 Rev 27/37

2 Communication layer

The SWIM is a single wire interface based on asynchronous, high sink (8 mA), open-drain,

bidirectional communication.

While the CPU is running, the SWIM allows non-intrusive read/write accesses to be performed on-the-fly to the RAM and peripheral registers, for debug purposes.In addition, while the CPU is stalled, the SWIM allows read/write accesses to be performed to any other part of the MCU’s memory space (Data EEPROM and program memory).CPU registers (A, X, Y , CC, SP) can also be accessed. These registers are mapped in memory and can be accessed in the same way as other memory addresses. ●Register, peripherals and memory can be accessed only when the SWIM_DM bit is set. ●When the system is in HALT , WFI or readout protection mode, the NO_ACCESS flag in the SWIM_CSR register is set. In this case, it is forbidden to perform any accesses because parts of the device may not be clocked and a read access could return garbage or a write access might not succeed.

The SWIM can perform a MCU device software reset.

The SWIM pin can also be used by the MCU target application as a standard I/O port with some restrictions if you also want to use it for debug. The safest way is to provide a strap option on the application PCB. Figure 2.

SWIM pin external connections

STM8

Application I/O

SWIM interface for tools

Jumper selection for

debug purposes

SWIM pin

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8/37Doc ID 14024 Rev 2

3

Single wire interface module (SWIM)3.1 Operating modes

After a Power-On Reset (powering of the device) the SWIM is reset and enters in its OFF mode.

1.OFF : In this mode the SWIM pin must not be used as an I/O by the application. It is

waiting for the SWIM entry sequence or to be switched to I/O mode by the application software.2. I/O : This state is entered by the software application by setting the IOM bit in the core configuration register (MCR). In this state, the user application can use the SWIM pin as a standard I/O pin, the only drawback is that there is no way to debug the functionality of this pin with the built-in debug capabilities. In case of a reset, the SWIM goes back to OFF mode.3. ACTIVE : This mode is entered when a specific sequence is detected on the SWIM pin while in OFF state. In this state, the SWIM pin is used by the host tool to control the STM8 with 3 commands. (SRST System Reset, ROTF Read On The Fly, WOTF Write On The Fly)

Note:

Please note that the SWIM can be set Active and communicate while the device is in RESET state (NRST pin forced low)Figure 3.

SWIM activation sequence

POR

ACTIVE

I/O

OFF

IOM bit set

Y

SWIM entry

sequence

Y

ROTF WOTF

RST bit set

reset

N

N

Y

N

CSR SRST

单总线通信接口模块

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6:,0 ω 2)) 在这个模式下,SWIM 脚不能被任务程序用作I/O ,它将等待SWIM 进入序列或者由应用软件切换到I/O 模式。I/O :应用程序可以置位内核配置寄存器(MCR )的IOM 位来进入这个模式。在这个模式

下,用户程序可以将SWIM 管脚用作标准I/O 管脚,唯一的缺点是无法使用内建的调试器来调试这个管脚的功能。

一旦复位,SWIM 将返回OFF 模式。

ACTIVE :在OFF 模式下,当SWIM 管脚上检测到一个特定的脉冲序列时,SWIM 将进入

ACTIVE 模式。在这个模式下,SWIM 管脚将被主机通过三条命令来控制STM8。(SRST 系统复位,ROTF 飞速读,WOTF 飞速写)注意SWIM 只有设备在RESET 状态下才可以被设置为ACTIVE 模式和通信(NRST 管脚强制为低)

Doc ID 14024 Rev 29/37

3.2 SWIM entry sequence After a POR, and as long as the SWIM is in OFF mode, the SWIM pin is sampled for entry

sequence detection. In order to do this, the internal low speed RC clock is automatically turned ON after POR and remains forced ON as long as the SWIM is in OFF mode.

If the register which forces the SWIM in I/O mode is written before the entry sequence is finalized, the SWIM enters I/O mode. Once the SWIM is ACTIVE, writing this bit has no influence on communication and the SWIM interface remains in ACTIVE mode.

If an application uses the SWIM pin as standard I/O, it puts the SWIM interface in I/O mode in the initialization section of the software code (typically, this is performed just after the reset). However, even in this case, it is still possible to put the SWIM interface in ACTIVE mode by forcing the RESET pin to 0 and keep it low for the duration of the SWIM entry sequence.As long as the SWIM is in OFF mode, the SWIM entry sequence is detected at any moment, during reset or when the application is running.If both the SWIM pin and the reset pin are multiplexed with I/Os, the way to enter SWIM ACTIVE state is to power down the MCU device, power up and to maintain the reset until the end of the SWIM entry sequence.6:,0

上电复位后,只要SWIM 处于OFF 模式下,SWIM 管脚就会被采样,直到检测到进入序列。为了达到这个目的,上电复位后,只要SWIM 处于OFF 模式下,内部低速RC 时钟自动启动并强制保持打开。如果在SWIM 检测到进入序列之前,配置SWIM 为I/O 模式的寄存器被置位,则SWIM 进入I/O 模式。一旦SWIM 进入ACTIVE 模式,配置SWIM 为I/O 模式为寄存器被置位也不影响通信,SWIM 接口将保存在ACTIVE 模式下。如果程序把SWIM 管脚作为标准I/O 使用,则软件代码初始化部分就要将SWIM 接口配置为I/O 模式(典型的是在复位之后)。然而,即使在这种情况下,强制使RESET 脚为0并保持为低直到SWIM 进入序列完成,也可以使SWIM 模块进入ACTIVE 模式。

只要SWIM 在OFF 模式下,SWIM 进入序列仍可以在任务时候被检测到,无论是复位期间还是

程序运行期间如果SWIM 脚和reset 脚都复用为IO ,则进入SWIM ACTIVE 状态的方法是使MCU 先掉电再上电来满足复位条件直到完成SWIM 的启动序列

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SWIM activation is shown in Figure 4 and each segment on the diagram is described below.1.

To make the SWIM active, the SWIM pin must be forced low during a period of 16 μs

(which is 64 pulses minimum at the frequency of HSI).

2. After this first pulse at 0, the SWIM detects a specific sequence to guarantee robustness in the SWIM active state entry. The SWIM entry sequence is: 4 pulses at 1 kHz followed by 4 pulses at 2 kHz. The frequency ratio is detected and allows SWIM entry. The ratio can be easily detected whatever the internal RC frequency. The waveform of the entry sequence is shown in Figure 5. Note that the sequence starts and ends with the SWIM pin at 1.

3. After the entry sequence, the SWIM enters in SWIM active state, and the HSI oscillator

is automatically turned ON. 4. After this delay, the SWIM sends a synchronization frame to the host.Synchronization frame description: A synchronization frame of 128 x HSI clock periods with the SWIM line at 0 is sent out by the MCU device to allow for the

measurement of the RC by the debug host. An advanced debug host can re-calibrate its clock to adapt to the frequency of Internal RC. 5. Before starting a SWIM communication, the SWIM line must be released at 1 to guarantee that the SWIM is ready for communication (at least 300 ns).6. Write 0A0h in the SWIM_CSR:- setting bit 5 allows the whole memory range and SRST command to be accessed.- setting bit 7 masks the internal reset sources 7. Release reset which starts the option byte loading sequence. Wait 1 ms for stabilization.

8. Once option byte loading has occurred and stabilization time is reached, the CPU is in

phase 8:

- STM8S is stalled and HSI = 16 Mhz (see STM8S datasheets for % accuracy)- SWIM clock is at HSI/2 = 8 Mhz - SWIM is active in low speed bit format (see Section 3.3.2)Figure 5.

SWIM entry sequence

SWIM pin

SWIM Active

1 ms

500 μs

SWIM entry sequence

6:,0 ζ?? 要使得SWIM 激活,SWIM 引脚必须保持低电平至少16us 在第一个0脉冲后,SWIM 检测到一个特定的序列以保证SWIM 进入活动状态,SWIM 的进入脉冲序列为:4个频率为1kHz 的脉冲,然后是4个频为1kHz 的脉冲.这些频率检测到才允许SWIM 进入。该比率可以很容易地被检测到不管是任何的内部RC 震荡频率。进入脉冲序列的波形见图5。注意,这个序列启动和结束时SWIM 脚的电平为1。

(即至少有HSI 中脉冲序列中的64个脉冲)在进入序列后,SWIM 进入SWIM 活动状态,HSI 振荡器自动打开。在这段延时之后,SWIM 发送一个同步帧给主机,同步帧说明:1个同步帧为128个HSI 时钟

周期,MCU 置SWIM 线为0电平,允许调试主机测量RC 振荡器。高级调试主机可以重复校准它的时钟来适应MCU 内部RC 震荡器的频率。SWIM 开始通信前,SWIM 线必须释放为1电平来保证SWIM 已做好通人 准备(至少300ns )。

SWIM_SCR 写入0xA0: -设置位5,使能整个内存空间和SRST 命令可以访问。 -设置位7,屏蔽内部复位源。

释放reset (置为低电平),启动选项字节加载序列。等待1ms 后到达稳定状态。

一旦选项字节加载且稳定状态时间达到,CPU 将进入阶段8:- STM8S 将暂停,HSI=16Mhz (见STM8S 数据表中的%精确性)

- SWIM 时钟为HSI/2 = 8Mhz

- SWIM 激活为低速位格式(见Section 3.3.2)

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3.3 Bit format The bit format is a Return-To-Zero format, which allows synchronization of every bit.Two communication speeds are available. At SWIM activation, the low speed is selected.

The high speed is selected by setting the HS bit in the SWIM_CSR register with the SWIM protocol.

When entering SWIM mode during the RESET phase, it is possible that the option bytes have not yet been loaded from non volatile memory to their respective registers.Option byte loading is triggered by any internal or external reset.

In order to ensure proper system behavior, the HS bit should not be set until the option byte loading is finished. At the end of the option byte loading, the HSIT bit in the SWIM_CSR is set by hardware.

3.3.1

High speed bit format 1 bit is generated with ten HSI oscillator pulses.The bit format is:

- 2 pulses at ‘0’ followed by 8 pulses at ‘1’ for ‘1’ value.

- 8 pulses at ‘0’ followed by 2 pulses at ‘1’ for ‘0’ value.

When the SWIM receives a data packet, it will decode:- ‘1’ when the number of consecutive samples at ‘0’ is less or equal to 4.- ‘0’ when the number of consecutive samples at ‘0’ is greater or equal to 5.Figure 6.

High speed bit format

<=> ‘1’

<=> ‘0’

位格式是一种回零格式,它允许任何一位为同步位。两种通信速率。在SWIM 激活时,为低速率。使用SWIM 协议设置SWIM_CSR 寄存器的HS 位,使能高速率。D RESET 阶段期间进入SWIM 模式时,选项字节可以还没有从内存加载到它们各自的寄存器中。任何内部或外部复位都会触发选项字节的加载。为了保证系统正确动作,HS 位必须被置位(设置为1),直到选项字节加载完成。在选项字节加载完成后,SWIM_CSR 寄存器的HSIT 位将将硬件置位。高速 位格式

10个HSI 振荡周期产生1位位格式为:

- 2个0脉冲后接着8个1脉冲代表 1。- 8个1脉冲后接着2个0脉冲代表 1。当SWIM 接收到一个数据包之后,它将自动解码:- 当连续采样到的0脉冲的个数小于等于4,则解码为1- 当连续采样到的0脉冲的个数大于等于5,则解码为1

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3.3.2

Low speed bit format 1 bit is generated with twenty-two HSI oscillator pulses.

The bit format is:

- 2 pulses at ‘0’ followed by 20 pulses at ‘1’ for ‘1’ value.

- 20 pulses at ‘0’ followed by 2 pulses at ‘1’ for ‘0’ value.

When the SWIM receives a data packet, it will decode:

- ‘1’ when the number of consecutive samples at ‘0’ is less or equal to 8.

- ‘0’ when the number of consecutive samples at ‘0’ is greater or equal to 9.

Figure 7.

Low speed bit format

<=> ‘1’

<=> ‘0’

低速 位格式

22位HSI 振荡周期产生1位位格式为:- 2个0脉冲后接着20个1脉冲代表 1。- 20个1脉冲后接着2个0脉冲代表 1。当SWIM 接收到一个数据包之后,它将自动解码:- 当连续采样到的0脉冲的个数小于等于8,则解码为1- 当连续采样到的0脉冲的个数大于等于9,则解码为1

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3.4 SWIM communication protocol When in ACTIVE mode, communication can be initiated by host or device. Each byte or

command is preceded by a 1-bit header in order to arbitrate if both host and device initiate the communication at the same time.

The host header is ‘0’ in order to have the priority over the device in case of arbitration, due to open-drain capability. The host can start the transfer only if there is no transfer on-going.Figure 8.

Command format (Host -> Target)

Each command sent by the host is made of:

● 1 command (ROTF , WOTF or SWRST) made of

Header: 1 bit at ‘0’b2-b0: 3-bit command pb: parity bit: XOR between all b(i)

ack:acknowledge (1 bit at ‘1’). The receiver must send the not-acknowledge value if it has detected a parity error (NACK: not acknowledge = 1 bit at ‘0’), or it is not yet ready.

optionally several data packets (in case of WOTF) made of:Header:1 bit at ‘0’b7-b0: 8-bit data pb: parity bit sent after data. XOR between all b(i)ack: acknowledge

Figure 9.

Data format (Target -> Host)

Each data frame is made of:

Header: 1 bit at ‘1’b7-b0: 8-bit data

pb: parity bit sent after data

ack: acknowledge

b2

b1

b0

ack Command

pb Data1

b7

b6

b5

b4

b3

b2

b1

b0

pb ack

...

...

Italic : Bit sent by the Host

Bold : Bit sent by the device

b7

b6b5b4b3b2b1b0pb ack

data n

data n+11...

...

data n-1

Italic : Bit sent by the Host Bold : Bit sent by the device

6:,0

在ACTIVE 模式下,主机和设备都可以发起通信。每个字节前都加入1个起始位以仲裁主机和设备同时开始通信。主机的起始位为0,使得发生仲裁冲突时,与从机相比主机拥有优先权,由于开漏性能。仅仅没有传输正在进行的时候,设备才可以启动转传输。每一条主机发送的命令的组成如下:1条命令(ROTF,WOTF 或者SWRST )组成如下:起始位:0

b2-b0:3位命令pb:奇偶校验位:XOR(所有的位b2-b0异或)ack:应答位(1),检测到奇偶校验出错或者接收没有准备好时,接收者必须发送0应答位的值

可选的若干数据包(在WOTF 命令时)组成如下:

起始位:0b7-b0: 8位数据pb:奇偶校验位:XOR(所有的位b7-b0异或)ack:应答位数据格式(目标到主机)起始位:1b7-b0:数据位pb :校验位,紧随数据位发送ack :应答位

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3.5 SWIM commands

The Host can send a command when the line is idle or after each data byte from device. After sending the command, the host releases the line. When the SWIM is ready to answer to the command, it initiates the transfer. If a new command from the host occurs while a command is pending in SWIM, the pending command is cancelled and the new command is decoded, except in case of WOTF .Three commands are available. They are listed in Table 1.

3.5.1 SRST: system reset

Format: 1 command from Host to Target

Parameters:

None.

SRST command generates a system reset only if SWIM_CSR/SWIM_DM bit is set.

3.5.2 ROTF: read on the fly

Format: 1 command followed by the number of bytes to be read followed by the address on three bytes.

Parameters:

N The 8 bits are the number of bytes to read (from 1 to 255)@E/H/L:This is the 24-bit address to be accessed.

D[...]: These are the data bytes read from the memory space

If the host sends a NACK to a data byte, the device will send the same byte again.If SWIM_DM bit is cleared, ROTF can only be done on SWIM internal registers.

Table 1.

SWIM command summary

Command Binary Code

SRST 000ROTF 001WOTF

010Reserved for future use

011

1xx

SRST

ROTF

N

@E

@H

@L

D[@]

D[@+N]

SWIM 命令字当总线空闲或者设备发送完所有数据时,主机可以发送命令字。发送完命令字后,主要将释放总线。当SWIM 准备好响应命令时,它会初始化传输。当S WIM 中有一条命令预备好时,如果此时接收到主机一条新的命令,则预备好的命令将被取消,而解码新的命令,除非是WOTF 命令。

有三条命令可用,如表1所示。SRST :系统复位格式:从主机到到目标参数:无SRST 命令仅仅在SWIM_CSR 的SWIM_DM 位被置位时才会产生系统复位。ROTF :读命令格式:读命令+需要读取的字节数+三个字节的地址参数:N 8位(1个字节)为需要读取的字节的个数(1-255)@E/H/L 这三个字节代表读取数据的内存的首地址D[....]: 这是从内存空间中读出来的数据如果主机在收到一个字节后发送一个NACK ,设备将重新发送这个字节。

如果SWIM_DM 位被清零,ROTF 将仅仅在SWIM 内部寄存器上完成。

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3.5.3 WOTF: write on the fly

1 command followed by the number of bytes to be written followed by the address on three bytes.

Parameters:

N The 8 bits are the number of bytes to write (from 1 to 255)

@E/H/L:This is the 24-bit address to be accessed.D[...]: These are the data bytes to write in the memory space If a byte D [i] has not been written when the following byte D [i+1] arrives, D [i+1] will be followed by a NACK. In this case the Host must send D [i+1] again until it is acknowledged. For the last byte, if it is not yet written when a new command occurs, the new command will receive a NACK and will not be taken into account.

If SWIM_DM bit is cleared, WOTF can only be done on SWIM internal registers.

3.6 SWIM communication reset

In case of a problem during communication, the host can reset the communication and the on-going command by sending 128 x HSI clock periods low on the SWIM pin. If the SWIM logic detects that the SWIM pin is low for more than 64 x HSI clock periods, it will reset the communication state machine and will switch the SWIM to low-speed mode

(SWIM_CSR.HS <- 0). This is to allow for variation in the frequency of the internal RC oscillator.

In response to this communication reset, SWIM will send the synchronization frame which is 128x HSI oscillator periods low on DBG pin.

WOTF

N

@E

@H

@L

D[@]

D[@+N]

WOTF:写命令格式:读命令+需要写入的字节数+三个字节的地址N 8位(1个字节)为需要写入的字节的个数(1-255)@E/H/L 这三个字节代表写入数据的内存的首地址D[....]: 这是要写入内存空间中的数据

如果D[i]还没有被写入而其后的D[i+1]已到达,D[i+1]将被回复一个NACK 。在这个 情况下,主机将重新发送D[i+1]直到收到应答。

如果最后一个字节还没有被写入,而又收到新的命令,则对新的命令将回得一个NACK ,且不执行新的命令。如果SWIM_DM 位被清零,ROTF 将仅仅在SWIM 内部寄存器上完成。SWIM 通信复位在通信异常发生时,主机可以通过在SWIM 管脚上发送128个HSI 时钟周期的低电平来复位这次通信和正在发送的命令。如果SWIM 逻辑检测到SWIM 管脚上持续64个HSI 时钟周期的低电平,SWIM 将复位通信,并且切换到低速模式。由于内部RC 振荡器可以分频才得以实现。SWIM 响应了通信复位之后,将发送同步帧(DBG 管脚的128个HSI 时钟周期的低电平)

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3.7 CPU register access

The CPU registers are mapped in the STM8 memory, and they can be read or written directly using the ROTF and WOTF SWIM commands. Write operations to the CPU registers are committed only when the CPU is stalled.

To flush the instruction decode phase, you must set the FLUSH bit in the DM control/status register 2 (DM_CSR2) after writing a new value in the Program Counter (PCE, PCH, PCL).

3.8 SWIM communication in Halt mode

To maintain the communication link with the debug host, the HSI oscillator remains on when the MCU enters Halt mode. This means that halt mode power consumption measurements have no meaning when the SWIM is active.

The NO_ACCESS bit in the SWIM_CSR register is set when the system is in HALT, WFI or readout protection mode. This means the bus is not accessible in this case.The OSCOFF bit in the SWIM_CSR register is used to switch off the oscillator. In this case, debug control is lost as long as the device is in Halt mode and the SWIM pin is high. The only way to recover the debug control is to induce a falling edge on SWIM pin: this will re-enable the HSI oscillator.

Table 2.

CPU register memory mapping in STM8

CPU register

Memory location

A 7F00h PCE 7F01h PCH 7F02h PCL 7F03h XH 7F04h XL 7F05h YH 7F06h YL 7F07h SPH 7F08h SPL 7F09h CC

7F0Ah

CPU 寄存器访问CPU 寄存器映射到STM8的内存中,它们通过SWIM 的ROTF 和WOTF 命令被正确的读写。只有CPU 暂停时,对CPU 寄存器的写操作才会有效和可靠。在刷新解码指令阶段中,你必须在对PC (程序计数器)写入新的值后设置DM_CSR2寄存器的FLUSH 位。CPU 寄存器内存映射在Halt 模式下的SWIM 通信为了维持与调试主机的通信连接,HSI 振荡器将保持振荡直到MCU 进入Halt 模式。这意味着当SWIM 激活时,对Halt 模式下功耗的测量将没有意义。系统在HALT 、WFI 或者写保护模式状态下时,SWIM_CSR 寄存器的NO_ACCESS 位将被置位。这意味着此时总线将无法访问。

SWIM_CSR 的OSCOFF 位用来关闭振荡器。在这个情况下,只要设备处于HALT 模式,SWIM 管脚为高电平,则无法进行调试。恢复调试控制唯一的方法是SWIM 管脚上捕获到下降沿:这个使得HSI 振荡器重新起振。

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3.9 Physical layer

During the communication, the SWIM pin will be in pseudo-open drain configuration. The SWIM pin in the device is capable of sinking 8 mA when it drives the line to 0. The external pull-up on the SWIM line should be sized in such a way that the maximum rise time t r of the SWIM line should be less than 1 sampling period of the bit (which is 100 ns +/- 4 %).Figure 10.Timings on SWIM pin

Table 3.

SWIM pin characteristics

Parameter

Symbol

Generic formula Timings for HSI = 10 MHz

LSI = 32 to 64 kHz Min

Max Fall time on SWIM pin t f TBD 50 ns Rise time on SWIM pin t r TBD 96 ns

Inter-bit time (The time which SWIM pin stays high between 2 bits)t ib

TBD

>0

Inter-frame time

(Time between end of a frame and the next one)t if

TBD 0Low time for a bit at 0

High speed: t b0TBD 768 ns 832 ns Low speed: t b0TBD 1.6 μs 2.4 μs Low time for a bit at 1(High Speed)

High speed: Tb1TBD 192 ns 208 ns Low speed: Tb1

TBD 150 ns

250 ns Injected current on SWIM pin

TBD

8 mA

t f

t r

t ib

SWIM pin

t b0/t b1

物理层在通信期间,SWIM 管脚将处于伪开漏模式,设备的SWIM 管脚低电平有8mA 的灌电流能力。SWIM 管脚的外部上拉必须满足,SWIM 管脚电平最大上升时间tr 必须小于1个数据位的采样周期(100ns +/-4%)SWIM 管脚下降时间SWIM 管脚上升时间跨位时间

(两个位之间SWIM 保持高电平时间)

跨帧时间 (一个帧结束与另一帧开始间隔时间)位0的低电平时间

位1的低电平时间 (高速)SWIM 管脚灌电流

3.10 STM8 SWIM registers

3.10.1 SWIM control status register (SWIM_CSR)

Address: 7F80h

Reset value: 00h

This register is reset only by a power on reset or by SWIM SRST command if the RST bit =1

in the SWIM_CSR register.

76543210 SAFE_MASK NO_ACCESS SWIM_D M HS OSCOFF RST HSIT PRI rw r rw rw rw rw r rw

Bit 7SAFE_MASK: Mask internal RESET sources

This bit can be read or written through SWIM only. It cannot be accessed through the STM8 bus. It includes the Watchdog reset.

0: Internal Reset sources are not masked

1: Internal reset sources are masked

Bit 6NO_ACCESS: Bus not accessible

This bit can be read through SWIM only, to determine the bus is accessible or not. It is set automatically if the device is in HALT, WFI or readout protection mode.

0: Bus is accessible

1: Bus is not accessible

Caution: Depending on the SWIM revision,in some devices, the NO_ACCESS bit indicates only that the device is in HALT mode.

Bit 5SWIM_DM: SWIM for Debug Module

This bit can be read or written to 1 through SWIM only. It cannot be accessed through the STM8 bus.

0: The SWIM can access only SWIM_CSR register. SWIM reset command has no effect

1: The whole memory range can be accessed with ROTF and WOTF commands. The SRST command generates a Reset

Bit 4HS: High Speed

This bit can be read or written through SWIM only. It cannot be accessed through STM8 bus.

0: Low speed bit format

1: High speed bit format

The speed change occurs when the communication is IDLE. It is reset by the SWIM communication reset condition as described in Section3.6.

Bit 3OSCOFF: Oscillators Off control bit

This bit can be read or written through SWIM only. It cannot be accessed through STM8 bus.

0: HSI oscillator remains ON in halt mode

1: HSI oscillator is not requested ON in Halt mode

STM8 SWIM寄存器

SWIM控制状态寄存器(SWIM_CSR)

地址:7F80H

复位值:00H

这个寄存器只有,在上电复位或者SWIM_CSR寄存器的RST位为1时执行SWIM的SRST命令

时,才会复位。

屏蔽内部RESET(复位源)

安全屏蔽位只能通过SWIM读写。不可以通过STM8总线访问。它屏蔽了包括

看门狗复位的复位源。

0:内部复位源没有被屏蔽

1:内部复位源被屏蔽

这个位只能通过SWIM访问,它决定了总线是否可以访问。当设备处于

HALT、WFI或者写保护模式中时,它将自动被置位。

0:总线可以访问

1:总线不可以访问

总线不可访问

调试模块的SWIM

这个位仅能通过SWIM读取或者置位。它不能通过STM8总线访问。

0:SWIM只可以访问SWIM_CSW寄存器。SWIM复位命令不生效。

1:整个内存空间都可以被ROTF和WOTF命令访问。SRST命令产生一个复

位。

高速

这个位只能通过SWIM读写。不可以通过STM8总线访问。

0:低速位格式

1:高速位格式

通信空闲时速率变化才会生效。3.6所描述的通信复位时,这个位也会被复位

振荡器关闭控制位

这个位只能通过SWIM读写。不可以通过STM8总线访问。

0:在HALT模式下,HSI振荡器保持打开

1:在HALT模式下,HSI振荡器不打开

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3.10.2 SWIM clock control register (CLK_SWIMCCR)Address Offset: 50CDh (product dependent)Reset value: xxxx 0000 (x0h)

Bit 2

RST : SWIM Reset Control Bit This bit can be read or written through SWIM only. It cannot be accessed through STM8 bus.0: SWIM is not reset when a SRST command occurs.1: SWIM is reset when a SRST command occurs. SWIM will re-enter OFF mode.Bit 1

HSIT : High Speed Internal Clock is trimmed This bit is read only through SWIM only. It cannot be accessed through STM8 bus. It is set when the HSIT bit is set in the core configuration register and reset by an external reset.0: High Speed Internal Clock is not trimmed, SWIM must remain in low speed mode.1: High Speed Internal Clock is trimmed, SWIM high speed mode is allowed.

Bit 0

PRI : SWIM access priority This bit can be read or written through SWIM only. Usually the SWIM accesses to system resources are non-intrusive, SWIM having the lowest priority. This can be overridden by setting this bit. 0: Non-intrusive access by SWIM to system resources (low priority)1: Intrusive access by SWIM to system resources (SWIM has priority, CPU is stalled). Note: The IOM bit is located in the STM8 core configuration register. Refer to the corresponding datasheet for information on this register

76543210Reserved

SWIMCLK

rw

Bits 7:1Reserved, must be kept cleared.

Bit 0

SWIMCLK SWIM clock divider

This bit is set and cleared by software.0: SWIM clock divided by 21: SWIM clock not divided by 2Note: this register is not present in some STM8 devices.

SWIM 复位控制位

这个位只能通过SWIM 读写。不可以通过STM8总线访问。 0:当收到SRST 命令时,SWIM 不复位

1:当收到SRST 命令时,SWIM 复位。SWIM 将再次进入OFF 模式

高速内部时钟被修正

这个位只能通过SWIM 读写。不可以通过STM8总线访问。内核寄存器的HSIT 位被置位时它也会被 置位,外部复位时,它也将复位。 0:高速内部钟没有被修正,SWIM 必须保持在低速模式下。

1:高速内部时钟被修正,SWIM 允许进入高速模式。

SWIM 访问优先级这个位只能通过SWIM 读写。通常SWIM 访问系统资源是非介入式的,SWIM 只有最低的优先权。设置这个位后,这一点将被忽视。 0:SWIM 以非介入式方式访问系统资源(低优先权)

1:SWIM 以介入式方式访问系统资源(SWIM 享有优先权,CPU 将被挂起) 注意:IOM 位位于STM8的内核配置寄存器。关于此寄存器的信息请参考相关的DATASHEET

SWIM 时钟控制寄存器(CLK_SWIMCCR )位置偏移:50CDH (决定于产品)复位值:xxxx 0000(x0h)保留,必须保持0SWIM 时钟分频器这个位可被软件置位和清除 0:SWIM 时钟二分频

1:SWIM 时钟非二分频 注意:有些STM8中没有这个寄存器

关于一些MATLAB用法和器件名称的中英文翻译

MATLAB - The Language Of Technical Computing MATLAB is a high-level language and interactive environment that enables you to perform computationally intensive tasks faster than with traditional programming languages such as C, C++, and Fortran. You can use MATLAB in a wide range of applications, including signal and image processing, communications, control design, test and measurement, financial modeling and analysis, and computational biology. Add-on toolboxes (collections of special-purpose MATLAB functions, available separately) extend the MATLAB environment to solve particular classes of problems in these application areas. MATLAB provides a number of features for documenting and sharing your work. You can integrate your MATLAB code with other languages and applications, and distribute your MATLAB algorithms and applications. MATLAB has key featuers as follows:(1)High-level language for technical computing (2)Development environment for managing code, files, and data(3)Interactive tools for iterative exploration, design, and problem solving 4)Mathematical functions for linear algebra, statistics, Fourier analysis, filtering, optimization, and numerical integration (5)2-D and 3-D graphics functions for visualizing data (6)Tools for building custom graphical user interfaces (7)Functions for integrating MATLAB based algorithms with external applications and languages, such as C, C++, Fortran, Java, COM, and Microsoft Excel The MATLAB language supports the vector and matrix operations that are fundamental to engineering and scientific problems. It enables fast development and execution. With the MATLAB language, you can program and develop algorithms faster than with traditional languages because you do not need to perform low-level administrative tasks, such as declaring variables, specifying data types, and allocating memory. In many cases, MATLAB eliminates the nee d for ‘for’ loops. As a result, one line of MATLAB code can often replace several lines of C or C++ code. At the same time, MATLAB provides all the features of a traditional programming language, including arithmetic operators, flow control, data structures, data types, object-oriented programming (OOP), and debugging features. MATLAB lets you execute commands or groups of commands one at a time, without compiling and linking, enabling you to quickly iterate to the optimal solution. For fast execution of heavy matrix and vector computations, MATLAB uses processor-optimized libraries. For general-purpose scalar computations, MATLAB generates machine-code instructions using its JIT (Just-In-Time) compilation technology. This technology, which is available on most platforms, provides execution speeds that rival those of traditional programming languages. MATLAB includes development tools that help you implement your algorithm efficiently. These include the following: MATLAB Editor - Provides standard editing and debugging features, such as setting breakpoints and single stepping. M-Lint Code Checker - Analyzes your code and recommends changes to improve its performance and maintainability. MATLAB Profiler - Records the time spent executing each line of code. Directory Reports- Scan all the files in a directory and report on code efficiency, file differences, file dependencies, and code coverage。 You can use the interactive tool GUIDE (Graphical User Interface Development Environment) to lay out, design, and edit user interfaces. GUIDE lets you include list

模块通信协议

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05-19200 06-38400 07-56700 08-115200 YY:00-无验证 01-验证 02-奇验证 //*************************************************************** **** 03读串口参数 //读串口参数 //AF AF 00 00 AF 80 02 LEN 00 00 CS 0D 0A //答应参数 //AF AF 00 00 AF 00 02 LEN XX YY CS 0D 0A XX:01-1200 02-2400 03-4800 04-9600 05-19200 06-38400 07-56700 08-115200 YY:00-无验证 01-偶验证 02-奇验证 //*************************************************************** **** 04设空中参数// //AF AF 00 00 AF 80 03 LEN XX YY CS 0D 0A //XX 01-1200 02-2400 03-4800 04-9600 05-19200 06-38400 07-56700 08-115200 YY=0 //答应参数 //AF AF 00 00 AF 00 03 LEN XX YY CS 0D 0A //XX 01-1200 02-2400 03-4800

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第一章绪论 由于希尔提出了1938肌肉的经典论文,神经生理学和神经肌肉骨骼系统的生物力学已被广泛研究,使人体运动生成的原理可以发现(希尔,1938)。 探讨中枢神经系统(CNS)激发肌肉和其后的发展力和产生不同的人体运动,许多模型来描述和定性的肌肉骨骼系统的不同层次的性能(温特斯,1990;扎杰克和温特斯,1990)。一个被普遍接受的山为基础的神经肌肉骨骼系统由以下子模型,一步一步:肌肉兴奋-收缩模型;肌腱骨骼模型;动态模型(扎耶克,1989)。 图1 肌肉骨骼模型框图 图1显示了基于hillbased模型的运动生成。图1,肌肉兴奋收缩模型是用来估计中枢神经系统指挥肌肉活动的状态。肌腱模型产生的肌肉力量不仅基于肌肉激活状态,而且基于肌腱式长度和肌腱式收缩速度,这与关节角速度和角速度(温特斯和斯塔克,1988)。前项状态的肌肉力量,它决定了肌腱的依从性,还负责肌肉力在后一阶段(扎耶克,1989)。一旦所有负责的关节运动的肌肉力量已经发现,肌肉的力量与各自的肌肉力臂和的结果求和乘法可以产生关节力矩。所有子模型的数学积分可以用来描述关节运动是中枢神经系统的命令产生哪些参数斧负责关节力矩。 肌电信号反映肌肉的活动,和许多类似的肌电力矩的关系已经在静态和动态情况的研究(张等人,1997;麦森纳和莫润,1995)。肌肉的肌电信号也常被认

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这些图片的窗口是从MA TLAB R2012b里面截图下来的,注释还不够全面。如有出入之处,敬请谅解!

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6 i CAN 6.1?? ? ?? i CAN? ?? ?Ё ?? ? ? ?CAN ?29? ?? ??????????? ??? ?? ? ? 6.1 ?? ? 6.1 ? ? ?? 1ˊ??? ?MAC ID? ??? ?MAC ID??? ???? ? ?? ??8??? ?0x00-0xFE?0xFF??????????? 254???? ?? Ё?? ? ??? ???? ? ??? ??? z SrcMACID (⑤??? )? ????? ? ?8?? ? ??0x00-0xFE? ⑤???ID z DestMACID (? ?? )? ???? ? ?8?? ? ??0x00-0xFF? DestID?0xFF ??? ? ?? ? ??? ㄨ? 2ˊACK? ??

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