Design and Detection of Hardware Trojan Horse Based on FPGA
A Dissertation Submitted for the Degree of Master
Candidate: Liu Huafeng Supervisor: Associate Prof. Jiang Xiaobo Senior Engineer Luo Hongwei
South China University of Technology
Guangzhou, China 分类号zTN4 学校代号：10561
学号：200921009803
华南理工大学硕士学位论文基于FPGA的硬件木马设计与检测
作者姓名：刘华锋申请学位级别：工程硕士研究方向：数字集成电路设计指导教师姓名、职称：姜小披副教授罗宏伟研究员学科专业名称：集成电路工程
论文提交日期：201 1年12月5日论文答辩归期：201 l年12月9日学位授予单位：华南理工大学学位授予H期：年月日寄辩委员会成员：主席：黄玄高级斗程师委员：李斌教授萎小波副教授吴朝晖副教授华南理工大学学位论文原创性声明
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作者签名：忑VI＼气b』日期：川叫年f主月7日'jJVj寸萨卡I
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作者签名：飞马玲』’期：.t.-<>ll1~－1
指导教师签名：本』价《期；
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ri.1 摘要由于半导体设计与制造过程的全球化，集成电路变得越来越容易受到恶意的行为和修改，集成电路在设计或制造过程中都可能会受到硬件木马的攻南，使芯片与硬件的安全性受到威胁。硬件木马技术已逐渐受到很大的重视，成为了当今一个新的研究热点。本文在FPGA的基础上进行了硬件木马电路的设计和检测工作，使用VerilogHDL 语言设计了多种硬件木马电路，并且完成了硬件木马测试系统的硬件设计。文章首先综述了本文研究工作的意义，硬件木马研究的发展现状，并且重点分析介绍了硬件木马的特性，硬件木马的分类与检测方法，以及未来的发展趋势。然后自主设计出f多组组合型和时序型硬件木马电路，并且通过了功能仿真和FPGA验证。之后，在此基础上实现了硬件木马测试系统的硬件设计，对测试方法与测试平台进行了不断的改进优化，对测试数据的处理方法进行了具体详细的讨论，并且对其中的关键技术和系统的功能模块做了详细的分析和介绍。最后对设计存在的不足与缺陷进行了总结和归纳。本文的贡献主要有两点：第一点是针对IP核的特点和结构，设计了若干种硬件木马电路，提出了术马电路的设计思路和方法。第二点是通过搭建基于电流检测电阻的硬件测试系统检测硬件木马，证明了基于功耗的旁路信号分析方法检测硬件木马是可行的，并且提出了自动测试系统检测电路旁路信号的思路和方法。
关键字：硬件木马：FPGA；集成电路：旁路分析ABSTRACT Because of globalization of the semiconductor design and fabrication process, integrated circuits are becoming increasingly vulnerable to malicious activities and alterations. Integrated circuits are vulnerable to hardware Trojans, which risk to chips and hardware,
either dw-ing design or fabrication. The Hardware Trojan technology has raised serious
concerns and become a new research focus. In this paper, design and detection of hardware Trojan horse are based on FPGA,
designed a variety of hardware Trojan horse, and finished the hardware design of test system In this paper, the author firstly summarized the significance of this research work, the current research status of hardware Trojan, and analyzed the characteristic of hardware Trojan, the
classification and the detection methods of hardware Trojan, and introduced the future trends
of hardware Trojan. Next, some Combinational and sequential Trojan circuits are designed, and successfully passed the functional simulation and FPGA verification. Fw-ther, the hardware design of test system was achieved , the detection method and the test system was improved continually, data processing methods were discussed in detail, the key technique and the realization of each function in this system were introduced and analysed. Finally, the 缸tideSW"llmarized the design shortcomings and defects .. The contributive points of this dissertation are: Fir前，designedsome hardware Trojans
according to the characteristic and the architecture of IP core , proposed the design ideas and
the design method of hardware Trojan. Second, hardware Trojans detected by the hardware test system based on the Current s巳nsingresistor, proved that based on the power of the side-channel signal analysis is feasible , and then proposed the ideas and methods about the automatic test system test the side-channel signal
keyword: hardware Trojan horse; FPGA; integrated circuit; side-channel signal
II 目录摘要..........…........………···············…..............…….....................……························……….............1
ABSTRACT ............................................................................................................................... 11 第一童绪论....................……...............…..............…….........….......…...............…....................1 1.1研究背景......................................................................................................................1 1.2硬件木马的发展现状.....................….........................................................................2 1.2.1硬件木马的定义...............................................................................................2 1.2.2硬件木马技术的发展现状.............................................................…................2 1.2.3硬件木马技术的发展趋势..............……........…………….......................…..........3 1.3课题研究的意义和主要研究内容...............................................…….........................4 1.4本章小结......................................................................................................................5 第二章硬件木马技术概述.......…...............…………...............…….......................................…..6 2.1硬件木马简介..............................................................................................................6 2.2硬件木马的分类..........................................................................................................7 2.3硬件木马的设计..............………·······························………........………..........................10