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数字系统设计技术实验指导书

Experiment 2 Designing Number Comparer实验目的: 熟悉QuartusII 的开发环境熟练掌握编程开发流程 学习VHDL 的基本语法 学习VHDL 编程设计实验内容:数值比较器设计实验要求:熟练掌握QuartusII 开发环境下对可编程逻辑器件进行程序化设计的整套流程设计输入使用插入模板(Insert Template )在QuartusII 开发环境下对设计程序进行时序仿真将生成的配置文件下载到实验板,进行最终的实物测试验证实验原理:根据两位二进制数的大小得到对应的比较结果,其电路示意图及电路特性表为:比较器特性表比较器电路示意图实验报告内容要求:(1) 实验目的;(2) 实验内容; (3) 实验要求; (4) 实验原理; (5) 程序编写; (6) 程序编译(首先选择器件具体型号); (7) 功能仿真和芯片时序仿真; (8) 芯片引脚设定; (9) 适配下载结果及结论。

NumberComparerA(3..0) B(3..0)In_s In_l In_eYl YeYs YExperiment 3 Designing 8 to1-Multiplxer实验目的:熟悉QuartusII的开发环境熟练掌握编程开发流程学习VHDL的基本语法学习VHDL编程设计实验内容:八选一数据选择器设计。

实验要求:熟练掌握QuartusII开发环境下对可编程逻辑器件进行程序化设计的整套流程设计输入使用插入模板(Insert Template)在QuartusII开发环境下对设计程序进行时序仿真将生成的配置文件下载到实验板,进行最终的实物测试验证实验原理:电路功能表及其电路外部符号如下:电路功能表实验报告内容要求:(1)实验目的;(2)实验内容;(3)实验要求;(4)实验原理;(5)程序编写;(6)程序编译(首先选择器件具体型号);(7)功能仿真和芯片时序仿真;(8)芯片引脚设定;(9)适配下载结果及结论。

Experiment 4 Designing module _60实验目的:熟悉QuartusII的开发环境熟练掌握编程开发流程学习数字系统中层次化设计技巧学习显示译码电路分频电路、计数电路的VHDL程序设计学习结构化设计的VHDL程序设计实验内容:基于数码管显示的60进制计数器设计实验要求:熟练掌握QuartusII开发环境下对可编程逻辑器件进行程序化设计的整套流程将50MHz信号分频为1Hz信号以1Hz为60进制计数器使能信号,实现60进制计数功能计数结果用两位数码管显示计数进位持续时间1s用LED显示设计位同步时序电路在QuartusII开发环境下对设计程序进行时序仿真将生成的配置文件下载到实验板,进行最终的实物测试验证实验原理:先对50MHz时钟信号分频得到1Hz,然后调用两个10进制计数器,计数到59时回到初始0的计数状态,每个10进制计数的技术结果通过显示译码送到两位数码管上显示,结构框图如下:50MHz数码管数码管(1) 实验目的; (2) 实验内容; (3) 实验要求; (4) 实验原理; (5) 程序编写;(6) 程序编译(首先选择器件具体型号); (7) 功能仿真和芯片时序仿真; (8) 结论。

Experiment 5 Designing shift_register实验目的: 熟悉QuartusII 的开发环境熟练掌握编程开发流程 学习VHDL 的基本语法学习数字系统中移位寄存器设计及其VHDL 编程实验内容:移位寄存器设计实验要求:熟练掌握QuartusII 开发环境下对可编程逻辑器件进行程序化设计的整套流程设计输入使用插入模板(Insert Template )在QuartusII 开发环境下对设计程序进行时序仿真将生成的配置文件下载到实验板,进行最终的实物测试验证实验原理:根据两位二进制数的大小得到对应的比较结果,其电路示意图及电路特性表为:比较器特性表比较器电路示意图Shift_registerSr slData_in(3..0) clk clr load ctrData_q(3..0)(9)实验目的;(10)实验内容;(11)实验要求;(12)实验原理;(13)程序编写;(14)程序编译(首先选择器件具体型号);(15)功能仿真和芯片时序仿真;(16)芯片引脚设定;(17)适配下载结果及结论。

实验2考程序Library ieee;Use ieee.std_logic_1164.all;Entity compare_2 isPort( data_a,data_b:in std_logic_vector(3 downto 0);In_s,In_l,In_e:in std_logic;Ys,Yl,Ye:out std_logic);End compare_2;Architecture rtl of compare_2 isSignal tmps,tmpe: std_logic;BeginYs<=tmps;Ye <= tmpe;Yl <= tmps nor tmpe;Aa:process(data_a,data_b, In_e)BeginIf(data_a = data_b and In_e = ‘1’) thentmpe<=’1’;elsetmpe<=’0’;End if;End process aa;bb:process(data_a,data_b, In_s)BeginIf(data_a<data_b) thentmps<=’1’;elsif(data_a=data_b and In_s=’1’) thentmps<=’1’;Elsetmps<=’0’;End if;End process bb;End rtl;实验3参考程序ENTITY mux8_1 ISPORT(d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);sb : IN STD_LOGIC;y : OUT STD_LOGIC);END mux8_1;ARCHITECTURE rtl OF mux8_1 ISBEGINPROCESS (d, sel,sb)BEGINIf(sb=’0’) thenCase(sel)When "000" => y<=d(0);When "001" => y<=d(1);When "010" => y<=d(2);When "011" => y<=d(3);When "100" => y<=d(4);When "101" => y<=d(5);When "110" => y<=d(6);When "111" => y<=d(7);When others => y<=’X’;end case;elsey<=’0’;end if;END PROCESS;END rtl;实体(entity)名称与文件名称一致;时序仿真时,波形编辑后先保存波形文件再进行时序仿真;分配管脚后,需要重现编译,然后才能下载。

设计流程:新建项目→新建源文件→输入语言→编译→仿真→分配管脚→编译→下载仿真流程:新建波形文件→导入管脚信号并编辑输入信号→仿真下载的时候选择硬件为:BytebBlaster[LPT1]实验4参考程序library ieee;use ieee.std_logic_1164.all;entity count_60 isport(clk,rst:in std_logic;count_data10,count_data1: out std_logic_vector(6 downto 0);en_out :out std_logic);end count_60;architecture rtl of count_60 iscomponent sec_out port(clk,rst:in std_logic;en_out :out std_logic);end component;component count_10 port(clk,rst,en_in,ld:in std_logic;data_in:in std_logic_vector(3 downto 0);data_out:out std_logic_vector(3 downto 0);en_out :out std_logic);end component;component dis_decode port(data_in:in std_logic_vector(3 downto 0);dis_num :out std_logic_vector(6 downto 0));end component;signal cont_tmp10,cont_tmp1,data_in:std_logic_vector(3 downto 0);signal ld,sec_en,sec_en10,min_out:std_logic;beginld<=sec_en10 and cont_tmp10(2) and cont_tmp10(0);data_in<="0000";en_out<=cont_tmp10(2) and cont_tmp10(0) and cont_tmp1(3) and cont_tmp1(0); U0:sec_out port map(clk,rst,sec_en);U1:count_10 port map(clk,rst,sec_en,ld,data_in,cont_tmp1,sec_en10);U2:count_10 port map(clk,rst,sec_en10,ld,data_in,cont_tmp10,min_out);U3:dis_decode port map(cont_tmp1,count_data1);U4:dis_decode port map(cont_tmp10,count_data10);end rtl;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity count_10 isport(clk,rst,en_in,ld:in std_logic;data_in:in std_logic_vector(3 downto 0);data_out:out std_logic_vector(3 downto 0);en_out :out std_logic);end count_10;architecture rtl of count_10 issignal cont_tmp:std_logic_vector(3 downto 0); beginen_out<=en_in and cont_tmp(3) and cont_tmp(0); data_out<=cont_tmp;process(clk,rst)beginif(rst='0')thencont_tmp<="0000";elsif(clk'event and clk='1')thenif(ld='1')thencont_tmp<=data_in;elsif(en_in='1')thenif(cont_tmp="1001")thencont_tmp<="0000";elsecont_tmp<=cont_tmp+'1';end if;end if;end if;end process;end rtl;library ieee;use ieee.std_logic_1164.all;entity dis_decode isport(data_in:in std_logic_vector(3 downto 0);dis_num :out std_logic_vector(6 downto 0)end dis_decode;architecture rtl of dis_decode isbeginwith data_in selectdis_num<="0111111" WHEN "0000","0000110" WHEN "0001","1011011" WHEN "0010","1001111" WHEN "0011","1100110" WHEN "0100","1101101" WHEN "0101","1111101" WHEN "0110","0000111" WHEN "0111","1111111" WHEN "1000","1100111" WHEN "1001","0000000" WHEN others;end rtl;library ieee;use ieee.std_logic_1164.all;entity sec_out isport(clk,rst:in std_logic;en_out :out std_logic);end sec_out;architecture rtl of sec_out iscomponent divide_5 port(clk,rst,en_in:in std_logic;en_out :out std_logic);end component;component divide_10 port(clk,rst,en_in:in std_logic;en_out :out std_logic);end component;signal en0,en1,en2,en3,en4,en5,en6:std_logic; beginU0:divide_5 port map(clk,rst,'1',en0);U1:divide_10 port map(clk,rst,en0,en1);U2:divide_10 port map(clk,rst,en1,en2);U3:divide_10 port map(clk,rst,en2,en3);U4:divide_10 port map(clk,rst,en3,en4);U5:divide_10 port map(clk,rst,en4,en5);U6:divide_10 port map(clk,rst,en5,en6);U7:divide_10 port map(clk,rst,en6,en_out); end rtl;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity divide_5 isport(clk,rst,en_in:in std_logic;en_out :out std_logic);end divide_5;architecture rtl of divide_5 issignal cont_tmp:std_logic_vector(2 downto 0); beginen_out<=en_in and cont_tmp(2);process(clk,rst)beginif(rst='0')thencont_tmp<="000";elsif(clk'event and clk='1')thenif(en_in='1')thenif(cont_tmp="100")thencont_tmp<="000";elsecont_tmp<=cont_tmp+'1';end if;end if;end if;end process;end rtl;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity divide_10 isport(clk,rst,en_in:in std_logic;en_out :out std_logic);end divide_10;architecture rtl of divide_10 issignal cont_tmp:std_logic_vector(3 downto 0);beginen_out<=en_in and cont_tmp(3) and cont_tmp(0); process(clk,rst)beginif(rst='0')thencont_tmp<="0000";elsif(clk'event and clk='1')thenif(en_in='1')thenif(cont_tmp="1001")thencont_tmp<="0000";elsecont_tmp<=cont_tmp+'1';end if;end if;end if;end process;end rtl;实验5参考程序library ieee;use ieee.std_logic_1164.all;ENTITY shift ISPORT(clr,clk,load,shift_en,ctr,sr,sl : IN STD_LOGIC;data_in : IN STD_LOGIC_VECTOR(7 downto 0);data_q : OUT STD_LOGIC_VECTOR(7 downto 0)); END shift;ARCHITECTURE arc OF shift ISSIGNAL data_tmp : STD_LOGIC_VECTOR(7 downto 0);Signal en_tmp1, en_tmp2, en_tmp: std_logic;BEGINPROCESS(clr,clk)BEGINIF (clr='0') THENen_tmp1 <=’0’;elseen_tmp1 <=shift_en;end if;end process;PROCESS(clr,clk)BEGINIF (clr='0') THENen_tmp2 <=’0’;elseen_tmp2<= en_tmp1;end if;end process;en_tmp<= (not en_tmp1) and en_tmp2;data_q<= data_tmp;PROCESS(clr,clk)BEGINIF (clr='0') THENdata_tmp <="00000000";ELSIF (clk'EVENT AND clk='1') THENIF load='0' THENdata_tmp <= data_in;ELSIF (en_tmp ='1' AND ctr='0') THENdata_tmp <=sr& data_tmp (7 downto 1);ELSIF (en_tmp ='1' AND ctr='1') THENdata_tmp <= data_tmp (6 downto 0) & sl;END IF;END IF;END PROCESS;END arc;。

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