signal up_r:std_logic; Begin Process(clk,rst) Begin IF rst='0' THEN
bcd_r<=(others=>'0'); up_r<='0'; ELSIF clk'EVENT AND clk='1' THEN IF bcd_r="00100100" THEN
bcd_r<=(others=>'0');up_r<='1'; ELSIF bcd_r(3 downto 0)="1001" THEN
bcd_r(3 downto 0)<="0000"; bcd_r(7 downto 4)<=bcd_r(7 downto 4)+1; up_r<='0'; ELSE bcd_r(3 downto 0)<=bcd_r(3 downto 0)+1; up_r<='0'; END IF; END IF; END PROCESS; bcd<=bcd_r; up<=up_r; END bhv;
实验原理
数字时钟框图如图17.1所示，一个完整的时钟应由4部分组成：秒 脉冲发生电路、计数部分、译码显示部分和时钟调整部分。
1、秒脉冲发生：一个时钟的准确与否主要取决秒脉冲的精确度。 可以设计分频电路对系统时钟50MHz进行50000000分频从而得到稳定的 1Hz基准信号。定义一个50000000进制的计数器，将系统时钟作为时钟 输入引脚clk，进位输出即为分频后的1Hz信号。
Begin IF rst='0' THEN
bcd_r<=(others=>'0'); up_r<='0'; ELSIF clk'EVENT AND clk='1' THEN IF bcd_r="01011001" THEN
bcd_r<=(others=>'0');up_r<='1'; ELSIF bcd_r(3 downto 0)="1001" THEN
END bhv;
数码管译码显示模块 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.பைடு நூலகம்TD_LOGIC_Arith.ALL; USE IEEE.STD_LOGIC_Unsigned.ALL; ENTITY xianshi IS PORT(
clk:IN STD_LOGIC; datain:IN STD_LOGIC_VECTOR(31 DOWNTO 0); dig,seg:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ENTITY;
ARCHITECTURE one OF xianshi IS SIGNAL counter: std_logic_vector(2 DOWNTO 0); SIGNAL display: std_logic_vector(3 DOWNTO 0);
SIGNAL seg_r: std_logic_vector(7 DOWNTO 0); SIGNAL dig_r: std_logic_vector(7 DOWNTO 0);
IF count="1000000000" THEN count<=(others=>'0'); clk_1Hz_r<=NOT clk_1Hz_r;
ELSE count<=count+1; END IF; END IF; END Process; clk_1Hz<=clk_1Hz_r; END bhv;
实验十七 数字时钟
实验目的
设计一个可以计时的数字时钟，其显示时间范围是 00:00:00~23:59:59，且该时钟具有暂停计时、清零等功能。
实验器材
1、SOPC实验箱 2、计算机（装有Quartus II 7.0软件）
实验预习
1、了解时钟设计原理和各主要模块的设计方法。 2、提前预习，编写好主模块的VHDL程序。
END PROCESS BBB;
CCC:PROCESS(counter,datain) BEGIN CASE counter IS WHEN "000" => display<=datain(31 DOWNTO 28); WHEN "001" => display<=datain(27 DOWNTO 24); WHEN "010" => display<=X"a"; WHEN "011" => display<=datain(19 DOWNTO 16); WHEN "100" => display<=datain(15 DOWNTO 12); WHEN "101" => display<=X"a"; WHEN "110" => display<=datain(7 DOWNTO 4); WHEN "111" => display<=datain(3 DOWNTO 0);
WHEN OTHERS =>NULL; END CASE; END PROCESS CCC;
DDD:PROCESS(display) BEGIN CASE display IS WHEN X"0"=> seg_r<=X"c0"; WHEN X"1"=> seg_r<=X"f9"; WHEN X"2"=> seg_r<=X"a4"; WHEN X"3"=> seg_r<=X"b0"; WHEN X"4"=> seg_r<=X"99"; WHEN X"5"=> seg_r<=X"92"; WHEN X"6"=> seg_r<=X"82"; WHEN X"7"=> seg_r<=X"f8"; WHEN X"8"=> seg_r<=X"80"; WHEN X"9"=> seg_r<=X"90"; WHEN X"a"=> seg_r<=X"BF"; --显示‘-’ WHEN X"b"=> seg_r<=X"83"; WHEN X"c"=> seg_r<=X"c6"; WHEN X"d"=> seg_r<=X"a1"; WHEN X"e"=> seg_r<=X"86"; WHEN X"f"=> seg_r<=X"8e"; WHEN OTHERS =>NULL; END CASE;
4、各模块连接方式如图17.1所示。
选择
显示码8位 数码管显示选通信号 6位
进位信号 进位信号
置数set 时钟信号 动态显示时钟信号2000Hz
译码 电路
数码管 小时 秒 分
60进制 计数器 60进制 计数器 24进制 计数器 复位rst
分频电路
系统时钟为1024Hz
图17.1 数字时钟框图
产生1Hz模块 Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; Entity clk_1Hz IS PORT(sys_clk:in std_logic;
2、计数部分：应设计1个60进制秒计数器、1个60进制分计数器、1 个24进制时计数器用于计时。秒计数器应定义clk（时钟输入）、 rst（复位）两个输入引脚，Q3~Q0（秒位）、Q7~Q4（十秒位）、 Co（进位位）9个输出引脚。分、时计数器类似。如需要设置时间可再 增加置数控制引脚Set和置数输入引脚d0~d7。
bcd_r(3 downto 0)<="0000"; bcd_r(7 downto 4)<=bcd_r(7 downto 4)+1; up_r<='0'; ELSE bcd_r(3 downto 0)<=bcd_r(3 downto 0)+1; up_r<='0'; END IF; END IF; END PROCESS; bcd<=bcd_r; up<=up_r;
BEGIN AAA:PROCESS(clk)
BEGIN IF clk'EVENT AND clk='1' THEN counter<=counter+1; END IF;
END PROCESS AAA;
BBB:PROCESS(counter) BEGIN CASE counter IS WHEN "000" => dig_r<="01111111"; WHEN "001" => dig_r<="10111111"; WHEN "010" => dig_r<="11011111"; WHEN "011" => dig_r<="11101111"; WHEN "100" => dig_r<="11110111"; WHEN "101" => dig_r<="11111011"; WHEN "110" => dig_r<="11111101"; WHEN "111" => dig_r<="11111110"; WHEN OTHERS =>NULL; END CASE;