嵌入式系统硬件设计SI基础
前言
SI挑战
现代电路设计不断朝高速、高密度、低电压、大电流趋势 发展，信号完整性（Signal Integrity，SI）、电源完整性 （Power Integrity，PI）和电磁兼容（Electromagnetic Compatibility，EMC）问题日益突出。传统设计方法显得力不 从心，需综合三者间相互影响进行协同设计.
Complex transient behavior related to the reflection coefficient on each extremities and transmission line discontinuities
反射解决方法

反射问题主要通过端接匹配解决，使信号在传输过程 中感觉不到瞬态阻抗突变。
Resistance at higher frequencies
When the conductor is much thicker than the skin depth one have to substitute the skin depth for the thickness in the resistance formula:
1.5
FFT(V(1))
1.5
FFT(V(1))
1.0
0.5
Y Axis Title [Volt]
0.2G 0.4G 0.6G 0.8G 1.0G
1.0
Amplitude [Volt]
0.5
0.0 0.0G
FREQ [Hz]
0.0 0.0G
0.2G
0.4G
0.6G
0.8G
1.0G
FREQ [Hz]
The effect of missing harmonics
At generator side (input): At generator side (input):
V z 0, t V t V t V 0, t 1 G
L L V z L, t V t V t V L, t 1 L v v
1.5
out1 l2out
1.0
Y Axis Title [Volt]
0.5
0.0
-0.5
-1.0 0.0n
10.0n
20.0n
30.0n
time [sec]
A digital signal
6.0
out
• Frequency 50MHz
• Risetime 1ns ( 10% 90% ) • Falltime 1ns ( 10% 90% )
1 0.75 0.5 0.5 0.25 0 0 -0.25 -0.5 -0.5 -0.75 -1
1st harmonic only
0.75 0.5 0.25 0 -0.25 -0.5 -0.75 0 2.5 5 7.5 10
0
2.5
5
7.5
10
12.5
15
17.5
1st to 5th harmonic
d s=

1 µf
[m]
Skin depth ( ds )
0.75 0.5 0.25 0 -0.25 -0.5 -0.75
0
2.5
5
7.5
10
12.5
15
17.5
1st and 3rd harmonic only
12.5
15
17.5
0
2.5
5
7.5
10
12.5
15
17.5
1st to 21st harmonic

反射
Signal integrity (SI) issue
Z0 =

R +L j G +C j
[ohm]
For a loss less line this simplifies to:
Z0 =

L C
[ohm]
Loss ( a )




Loss a is measured in dB / m Loss is the reduction of signal voltage along a line due to resistance and leakage The resistive losses is due to resistance in conductor and ground plane. The dielectric losses is due to the energy needed to change polarization of the dielectric material. The radiation losses is the energy sent from the conductor acting as an antenna.
Aplitude [Volt]
0.2
0.2
0.1
0.1
0.0 0.0M
50.0M
100.0M
150.0M
0.0 0.0M
50.0M
100.0M
150.0M
200.0M
FREQ [Hz]
FREQ [Hz]
10 ns risetime
1 ns risetime
Spectrum of a pulse train

抖动-实际信号与理想信号间的时序波动， 由系统内在噪声和外在噪声共同引起。
串扰

串扰-串扰是指多信号网络间边缘场耦合效应导致的噪声干扰现象。
串扰

高速电路中需要控制串扰的布线网络 主要包括：高速并行总线、高速时钟总 线、高速接插件等。常用的减小串扰措 施包括：减小平行走线长度、增大线间 距、采用平面作返回路径、减小互连特 性阻抗以及采用防护布线等。
R=
1
ds
1
[ohm]
R=


1 µf
The resistance has now become frequency dependent !
Skin depth ( ds )
At higher frequencies only a thin layer of the conductor transport the current. The thickness where the current density is reduced to 1/e is called the skin depth ds.
SI挑战

SI问题是电路高速化的产物，电路高 速化指电路中信号的有效带宽增加，主 要表现在系统工作频率提高和数字信号 边沿率加快两方面。高速电路常见的SI 问题包括：反射（Reflection）、串扰 （Crosstalk）、同时开关噪声（SSN， Simultaneous Switching Noise）、时序 错位与抖动（Timing Skew & Jitter）等
z z V z, t V t V t v v 1 z 1 z I z, t V t V t ZC v ZC v 1 1 v lc

The voltage at each point of the line depends on the reflection coefficient at each line terminals:
Impedance ( Z0 )

Impedance is measured in Ohms Impedance describes the AC resistance a driver will see when driving a signal into a indefinitely long transmission line.
0
L
z
ZG
I(z,t)
++++++Interconnect
VG
l ZC ------- c
I(z,t)
Load
ZL
Thevenin generator
Transmission line

The voltage and current on each point of the line is superposition of a forward and backward voltage, travelling in opposite directions.
5.0
Voltage [Volt]
3.0
• Bandwidth 350MHz
1.0
-1.0 0.0n
10.0n
20.0n
30.0n
time [sec]
Spectrum of a single pulse
0.4
FFT(V(1))
0.4
FFT(V(1))
0.3
0.3
Y Axis Title [Volt]
L V t v Z L ZC L L Z L ZC V t v
V t ZG ZC G V t ZG ZC

Transient behavior of voltage at each line terminals:
Basic transmission line
Driver
Transmission line
Termination resistor
The four describing parameters


R C L G