© 2001 by Prentice Hall
Photoresist Development Problems
Resist Substrate
X
X

X
Under develop
Incomplete develop
Correct develop
Severe overdevelop
Semiconductor Manufacturing Technology
Semiconductor Manufacturing Technology
Michael Quirk & Julian Serda © October 2001 by Prentice Hall
Chapter 15
Photolithography: Resist Development and Advanced Lithography
PAC
PAC
PAC
PAC PAC PAC PAC PAC PAC
PAC
PAC
PAC
(a) Exposure to UV light
PAC PAC PAC PAC PAC PAC PAC PAC PAC PAC PAC PAC PAC PAC PAC
(b) Striations in resist
PAC
• Continuous Spray Development • Puddle Development
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
© 2001 by Prentice Hall
Resist Development with Continuous Spray
Develop
• • • •
Negative Resist Positive Resist Development Methods Resist Development Parameters
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Photoresist
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 15.8
© 2001 by Prentice Hall
Develop Inspect • • • • Post-Develop Inspection to Find Defects Find Defects before Etching or Implanting Prevents Scrap Characterizes the Photo Process by Providing Feedback Regarding Quality of the Lithography Process • Develop Inspect Rework Flow
– Evaporates Residual Solvent in Photoresist
– Hardens the Resist
– Improves Resist-to-Wafer Adhesion – Prepares Resist for Subsequent Processing
– Higher Temperature than Soft Bake, but not to Point Where Resist Softens and Flows
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
© 2001 by Prentice Hall
Objectives
After studying the material in this chapter, you will be able to: 1. Explain why and how a post exposure bake is done for conventional and Chemically amplified DUV resist. 2. Describe the negative and positive resist development process for conventional and chemically amplified DUV resist. 3. List and discuss the two most common resist development methods and the critical development parameters. 4. State why a hard bake is done after resist development. 5. Explain the benefits of a post-develop inspection. 6. List and describe the four different alternatives for advanced lithography, including the challenges for introducing each alternative into production. 7. Describe and give the benefit for the advanced resist process of top surface imaging.
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
© 2001 by Prentice Hall
Amine Contamination of DUV Resist leading to “T-top” Formation
• Resist Hardening with Deep UV
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
© 2001 by Prentice Hall
Softened Resist Flow at High Temperature
by Michael Quirk and Julian Serda
Figure 15.4
© 2001 by Prentice Hall
Development of Positive Resist
Resist exposed to light dissolves in the develop chemical.
PAC
(c) PEB causes PAC diffusion
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
(d) Result of PEB
Figure 15.2 © 2001 by Prentice Hall
Region of unexposed photoresist
Neutralized photoresist
}
H+ H+
Resist T-topping
H+ PAG H+ H+ H+ PAG
PAG PAG PAG PAG PAG
Development
H+
H+ H+
H+
PAG
Acid-catalyzed reaction of exposed resist (post PEB)
(a) Wafer track system
(b) Developer spray dispenser
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 15.6
© 2001 by Prentice Hall
Unexposed positive resist
Crosslinked resist
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
Figure 15.5
© 2001 by Prentice Hall
Development Methods
by Michael Quirk and Julian Serda
Table 15.1
© 2001 by Prentice Hall
Post Exposure Bake
• Deep UV Exposure Bake
– Temperature Uniformity – PEB Delay
• Conventional I-Line PEB
Puddle Resist Development
Puddle formation Developer dispenser
(a) Puddle dispense
(b) Spin-off excess developer
(c) DI H2O rinse
Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda
(d) Spin dry
Figure 15.7 © 2001 by Prentice Hall
Resist Developmeveloper Temperature Developer Time Developer Volume Normality Rinse Exhaust Flow Wafer Chuck