writereg MBAR 0xFF400000writemem.l 0xFF400000 0xE0000000 # IMMRBAR = 0xE0000000writereg MBAR 0xE0000000writemem.l 0xE0000020 0xFE000000# LBLAWBAR0 - begining at 0xfe000000 writemem.l 0xE0000024 0x80000014# LBLAWAR0 - enable, size = 2MB#writemem.l 0xE0000028 0xFA000000 # LBLAWBAR1 FPGAbegining at 0xfa000000#writemem.l 0xE000002C 0x8000000E # LBLAWAR1 - enable, size = 32KB writemem.l 0xE00000A0 0x00000000 # DDRLAWBAR0 - begining at 0x00000000 writemem.l 0xE00000A4 0x80000018 # DDRLAWAR0 - enable, size = 32MB# DDR Controller Configuration#1 DDRCDRwritemem.l 0xE0000128 0x73040002#CLK_CNTLwritemem.l 0xE0002130 0x02000000#同原0x02000000。

[5-7]CLK_ADJST = 010（1/2），or 011（3/4）# CS0_BNDSwritemem.l 0xE0002000 0x00000001 # 0x00000001 - 0x01FFFFFF ;32MB# CS0_CONFIG# [8]AP_0_EN = 1，0？# [16-17]BA_BITS_CS_0 = 00，01? Number of bank bits for SDRAM on chip select n.# [21-23]ROW_BITS_CS_0 = b'001' ; 12 row bits# [29-31]COL_BITS_CS_0 = b'010' ; 9 columns bits#原0x80840102 不同：[29-31]、[21-23]，writemem.l 0xE0002080 0x80000001# TIMING_CFG_3 原0x00000000# 13-15EXT_REFREC = 001; AUTO REFRESH command period tRFC=72 ns writemem.l 0xE0002100 0x00010000# TIMING_CFG_1 原0x26256222# bit 1-3 = 2 tRP=15ns，(tck=7.5) （类似tRP ，为DDR芯片手册上内容）# bit 4-7 = 6 tRAS=42ns，# bit 9-11 = 2 tRCD=15ns，# bit 12 - 15 = 0011:2；0100:2.5# bit 16 - 19 = 2 (10tck) tRFC=72 ns (tck=7.5)# bit 21 - 23 = 2 tWR=15ns，# bit 25 - 27 = 2 tRRD=12ns，# bit 29 - 31 = 1 tWTR=1tckwritemem.l 0xE0002108 0x26232221# TIMING_CFG_2 原0x0f9028c7# bit 4-8 =11111 OR 00010 DQS read preamble tRPRE=0.9tck# bit 16-18=100 010(BL=4) OR 100(BL=8)# bit 19-21 = b'011' Write command to write data strobe timing adjustment # 3/4 DRAM clock delay#Write command to first DQS latching transition tDQSS=0.75 writemem.l 0xE000210C 0x0F888C41# TIMING_CFG_0 原0x00220802# [9-11]ACT_PD_EXIT = b'001' ; 1 Clocks P46(MT46V8M16P_6T.pdf) # [13-15]PRE_PD_EXIT = b'001' ; 1 Clocks# [28-31]MRS_CYC = b'0010'=2CLOCKS;tMRD=12writemem.l 0xE0002104 0x00220002# temporary disable DDR_SDRAM_CFG 原0x43080000# [1]SREN = b'1'# [3]RD_EN = b'0'# [10]DYN_PWR = b'0'# [11-12]DBW = b'01' DRAM data bus width：01=32bit，10=16bit # [13]8_BE = b'1' 0=4-beat bursts 1=8-beat bursts#[14] NCAP = b'0' 0= support concurrent auto-precharge# [16]2T_EN = b'0'# [26]x32_EN = b'0'# [27]PCHB8 = b'0'# [28]HSE = b'0'# [30]MEM_HALT = b'0'# [31]BI = b'0'writemem.l 0xE0002110 0x420C0000# DDR_SDRAM_CFG_2 原0x00401000# [0]FRC_SR = b'0'# [2] DLL_RST_DIS = b'0'# [16-19]NUM_PR = b'0001'# [27]D_INIT = b'0' DRAM data initialization (or 1？！) writemem.l 0xE0002114 0x00001000#DDR_SDRAM_MODE 原0x44400232#[0-15] ESDMODE=4000#[16-31] SDMODE=0023, Burst Length=8, CAS Latency=2 writemem.l 0xE0002118 0x40000023# DDR_SDRAM_INTERV AL 原0x03200064# [0-15]REFINT = 2600 Clocks,# [18-31] BSTOPRE = 000, auto-prechargewritemem.l 0xE0002124 0x03200064#delay before enablesleep 300# enable the DDR memory controller DDR_SDRAM_CFGwritemem.l 0xE0002110 0xC20C0000############################################### Local Bus Interface (LBIU) Configuration############################################### Local bus CS0 - NOR Flash settings# BR0 base address at 0xFE000000, port size 16 bit, GPCM, validwritemem.l 0xE0005000 0xFE001001writemem.l 0xE0005004 0xFFE00FF7 # OR0 16Mbit，flash size, 15 w.s., timing relaxed# Local bus CS1 – FPGA settings 32Kbwritemem.l 0xe0005010 0xFA001001# BR1 base address at 0xF8000000, port size 16 bit, GPCM, validwritemem.l 0xe0005014 0xFFFF8FF7 # OR1 32KB# LBCR - local bus enablewritemem.l 0xE00050D0 0x00000000# LCRR# bit 14 - 15 = 0b11 - EADC - 3 external address delay cycles# bit 28 - 31 = 0x0010 - CLKDIV - system clock: memory bus clock = 2writemem.l 0xE00050d4 0x00030002# MRTPR - refresh timer prescalerwritemem.l 0xE0005084 0x20000000writereg MSR 0x2000 # FP available, machine check disable, exception vectors at 0x0000_0000 writemem.l 0xE0000800 0x00000000# ACR - Enable Core_______________________________________________________________________________ 说明：Memory map and initialization0x00000000 - 0x01FFFFFF - 32MB DDR0xE0000000 - 0xE00FFFFF - 1MB Internal Memory Register Space 内部存储器寄存器空间0xFA000000 - 0xFA000FFF - 4KB FPGA0xFE000000 - 0xFE1FFFFF - 2MB NOR FlashClocksCore_CLK : 333 MHz 不确定CSB_CLK : 166 MHz 不确定DDR_CLK : 333 MHz 不确定PIC_CLK : 33 MHz 确定Reset Configuration Words 阅读先前程序所得RCWLR ：0x65040000 ；SPMF->5:1，Corrpll->2:1RCWHR ：0x20603800 ；电路连接：8313的MEMC_MCS0# 并联连接两个MT46V8M16PET，128Mbit。