C0
C7
00000081
03
CAR<=XXXX
C1
00000002
STORE X
08
CAR<=CAR+1
PC<=PC+1
MAR<=MBR[L8]
C0
C8
C6
00000141
09
CAR<=CAR+1
MBR<=ACC
C0
C12
00001001
0A
CAR<=0
MEMORY<=MBR
C2
C4
00000014
c(22)
undefined
c(23)
undefined
c(24)
undefined
c(25)
undefined
c(26)
undefined
c(27)
undefined
c(28)
undefined
c(29)
undefined
c(30)
undefined
c(31)
undefined
Table3The Sequence of Microinstructions
00001101
0D
ACC>>1 =>ACC
SHIFTL
00001110
0E
ACC<<1 =>ACC
STORE MR [x]
00001111
0F
MR=>[X]
Table2The meaning of each bit of the microinstruction
c (0)
CAR<=CAR+1
c (1)
Table 1 List of instructions and relevant opcodes
INSTRUCTION
OPCODE(Binary)
OPCODE(Hex)
COMMENTS
STORE X
00000001
01
ACC=>[X]
LOAD X
00000010
02
[X]=>ACC
ADD X
00000011
03
ACC+[X]=>ACC
SUB X
t;ACC
JMPGEZ X
00000101
05
if ACC>=0, X=>PC
else PC+1=>PC
JMP X
00000110
06
X=>PC
HALT
00000111
07
Halt a program
MPY X
00001000
08
C0
C3
00000009
1A
CAR<=CAR+1
BR<=MBR
C0
C9
00000201
1B
CAR<=CAR+1
ALU<=BR
ALU<=ACC
C0
C20
C14
00104001
1C
CAR<=CAR+1
ALU_Calculate
C0
C15
00008001
1D
CAR<=0
ACC<=ALU
C2
C13
00002004
41
CAR<=CAR+1
MBR<=MR
C0
C18
00040001
42
CAR<=0
MEMORY<=MBR
C2
C4
00000014
CAR<= XXXX
c(2)
CAR<=0
c(3)
MBR<=MEMORY
c(4)
MEMORY<=MBR
c(5)
MAR<=PC
c(6)
MAR<=MBR(L8)
c(7)
IR<=MBR(H8)
c(8)
PC<=PC+1
c(9)
BR<=MBR
c(10)
ACC<=0
c(11)
ACC<=MBR
c(12)
MBR<=ACC
C0
C20
C14
00104001
14
CAR<=CAR+1
ALU_Calculate
C0
C15
00008001
15
CAR<=0
ACC<=ALU
C2
C13
00002004
ADD X
18
CAR<=CAR+1
PC<=PC+1
MAR<=MBR[L8]
C0
C8
C6
00000141
19
CAR<=CAR+1
MBR<=MEMORY
LOAD X
10
CAR<=CAR+1
PC<=PC+1
MAR<=MBR[L8]
C0
C8
C6
00000141
11
CAR<=CAR+1
MBR<=MEMORY
C0
C3
00000009
12
CAR<=CAR+1
ACC<=0
BR<=MBR
C0
C10
C9
00000601
13
CAR<=CAR+1
ALU<=BR
ALU<=ACC
00104001
3C
CAR<=CAR+1
ALU_Multiply
C0
C16
00010001
3D
CAR<=0
MR<=ALU[H16]
ACC<=ALU[L16]
C2
C17
C13
00022004
STORE MR [X]
40
CAR<=CAR+1
PC<=PC+1
MAR<=MBR[L8]
C0
C8
C6
00000141
JMPGEZ X
20
CAR<=CAR+1+FLAG
C21
00200000
21
CAR<=0
PC<=MBR[L8]
C2
C19
00080004
22
CAR<=0
PC<=PC+1
C2
C8
00000104
JMP X
28
CAR<=0
PC<=MBR[L8]
C2
C19
00080004
HALT
30
CAR<=0
C2
00000004
MPY X
38
CAR<=CAR+1
PC<=PC+1
MAR<=MBR[L8]
C0
C8
C6
00000141
39
CAR<=CAR+1
MBR<=MEMORY
C0
C3
00000009
3A
CAR<=CAR+1
BR<=MBR
C0
C9
00000201
3B
CAR<=CAR+1
ALU<=BR
ALU<=ACC
C0
C20
C14
Instruction
Address(Hex)
Micro-instruction
Control_Signals
Code(Hex)
FETCH
00
CAR<=CAR+1
MAR<=PC
C0
C5
00000021
01
CAR<=CAR+1
MBR<=MEMORY
C0
C3
00000009
02
CAR<=CAR+1
IR<=MBR[H8]
c(13)
ACC<=ALU
c(14)
ALU<=ACC
c(15)
ACC_Calculate(+—/ and or not shiftr shiftl)
c(16)
ALU_Multiply
c(17)
MR<=ALU
c(18)
MBR<=MR
c(19)
PC<=MBR[L8]
c(20)
ALU<=BR
c(21)
CAR<=CAR+1+FLAG
ACC*[X]=>ACC(L16)
ACC*[X]=>MR(H16)
DIV X
00001001
09
ACC/[X]=>ACC
AND X
00001010
0A
ACC and [X]=>ACC
OR X
00001011
0B
ACC or [X]=>ACC
NOT X
00001100
0C
not [X]=>ACC
SHIFTR